developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2022 MediaTek Inc. |
| 4 | * Author: Sam Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #include <dt-bindings/interrupt-controller/irq.h> |
| 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 9 | #include <dt-bindings/phy/phy.h> |
| 10 | #include <dt-bindings/clock/mt7986-clk.h> |
| 11 | #include <dt-bindings/reset/mt7629-reset.h> |
| 12 | #include <dt-bindings/pinctrl/mt65xx.h> |
| 13 | |
| 14 | / { |
| 15 | compatible = "mediatek,mt7986"; |
| 16 | interrupt-parent = <&gic>; |
| 17 | #address-cells = <1>; |
| 18 | #size-cells = <1>; |
| 19 | |
| 20 | config { |
| 21 | u-boot,mmc-env-partition = "u-boot-env"; |
| 22 | }; |
| 23 | |
| 24 | cpus { |
| 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; |
| 27 | cpu0: cpu@0 { |
| 28 | device_type = "cpu"; |
| 29 | compatible = "arm,cortex-a53"; |
| 30 | reg = <0x0>; |
| 31 | mediatek,hwver = <&hwver>; |
| 32 | }; |
| 33 | cpu1: cpu@1 { |
| 34 | device_type = "cpu"; |
| 35 | compatible = "arm,cortex-a53"; |
| 36 | reg = <0x1>; |
| 37 | mediatek,hwver = <&hwver>; |
| 38 | }; |
| 39 | cpu2: cpu@2 { |
| 40 | device_type = "cpu"; |
| 41 | compatible = "arm,cortex-a53"; |
| 42 | reg = <0x2>; |
| 43 | mediatek,hwver = <&hwver>; |
| 44 | }; |
| 45 | cpu3: cpu@3 { |
| 46 | device_type = "cpu"; |
| 47 | compatible = "arm,cortex-a53"; |
| 48 | reg = <0x3>; |
| 49 | mediatek,hwver = <&hwver>; |
| 50 | }; |
| 51 | }; |
| 52 | |
| 53 | dummy_clk: dummy12m { |
| 54 | compatible = "fixed-clock"; |
| 55 | clock-frequency = <12000000>; |
| 56 | #clock-cells = <0>; |
| 57 | /* must need this line, or uart uanable to get dummy_clk */ |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 58 | bootph-all; |
developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 59 | }; |
| 60 | |
| 61 | hwver: hwver { |
| 62 | compatible = "mediatek,hwver", "syscon"; |
| 63 | reg = <0x8000000 0x1000>; |
| 64 | }; |
| 65 | |
| 66 | timer { |
| 67 | compatible = "arm,armv8-timer"; |
| 68 | interrupt-parent = <&gic>; |
| 69 | clock-frequency = <13000000>; |
| 70 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 71 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 72 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 73 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| 74 | arm,cpu-registers-not-fw-configured; |
| 75 | }; |
| 76 | |
| 77 | timer0: timer@10008000 { |
| 78 | compatible = "mediatek,mt7986-timer"; |
| 79 | reg = <0x10008000 0x1000>; |
| 80 | interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; |
| 81 | clocks = <&infracfg CK_INFRA_CK_F26M>; |
| 82 | clock-names = "gpt-clk"; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 83 | bootph-all; |
developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 84 | }; |
| 85 | |
| 86 | watchdog: watchdog@1001c000 { |
| 87 | compatible = "mediatek,mt7986-wdt"; |
| 88 | reg = <0x1001c000 0x1000>; |
| 89 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 90 | #reset-cells = <1>; |
| 91 | status = "disabled"; |
| 92 | }; |
| 93 | |
| 94 | gic: interrupt-controller@c000000 { |
| 95 | compatible = "arm,gic-v3"; |
| 96 | #interrupt-cells = <3>; |
| 97 | interrupt-parent = <&gic>; |
| 98 | interrupt-controller; |
| 99 | reg = <0x0c000000 0x40000>, /* GICD */ |
| 100 | <0x0c080000 0x200000>; /* GICR */ |
| 101 | |
| 102 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 103 | }; |
| 104 | |
| 105 | fixed_plls: apmixedsys@1001E000 { |
| 106 | compatible = "mediatek,mt7986-fixed-plls"; |
| 107 | reg = <0x1001E000 0x1000>; |
| 108 | #clock-cells = <1>; |
| 109 | }; |
| 110 | |
| 111 | topckgen: topckgen@1001B000 { |
| 112 | compatible = "mediatek,mt7986-topckgen"; |
| 113 | reg = <0x1001B000 0x1000>; |
| 114 | clock-parent = <&fixed_plls>; |
| 115 | #clock-cells = <1>; |
| 116 | }; |
| 117 | |
| 118 | infracfg_ao: infracfg_ao@10001000 { |
| 119 | compatible = "mediatek,mt7986-infracfg_ao"; |
| 120 | reg = <0x10001000 0x68>; |
| 121 | clock-parent = <&infracfg>; |
| 122 | #clock-cells = <1>; |
| 123 | }; |
| 124 | |
| 125 | infracfg: infracfg@10001040 { |
| 126 | compatible = "mediatek,mt7986-infracfg"; |
| 127 | reg = <0x10001000 0x1000>; |
| 128 | clock-parent = <&topckgen>; |
| 129 | #clock-cells = <1>; |
| 130 | }; |
| 131 | |
| 132 | pinctrl: pinctrl@1001f000 { |
| 133 | compatible = "mediatek,mt7986-pinctrl"; |
| 134 | reg = <0x1001f000 0x1000>, |
| 135 | <0x11c30000 0x1000>, |
| 136 | <0x11c40000 0x1000>, |
| 137 | <0x11e20000 0x1000>, |
| 138 | <0x11e30000 0x1000>, |
| 139 | <0x11f00000 0x1000>, |
| 140 | <0x11f10000 0x1000>, |
| 141 | <0x1000b000 0x1000>; |
| 142 | reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", |
| 143 | "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", |
| 144 | "iocfg_tl_base", "eint"; |
| 145 | gpio: gpio-controller { |
| 146 | gpio-controller; |
| 147 | #gpio-cells = <2>; |
| 148 | }; |
| 149 | }; |
| 150 | |
| 151 | pwm: pwm@10048000 { |
| 152 | compatible = "mediatek,mt7986-pwm"; |
| 153 | reg = <0x10048000 0x1000>; |
| 154 | #clock-cells = <1>; |
| 155 | #pwm-cells = <2>; |
| 156 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| 157 | clocks = <&infracfg CK_INFRA_PWM>, |
| 158 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| 159 | <&infracfg_ao CK_INFRA_PWM1_CK>, |
| 160 | <&infracfg_ao CK_INFRA_PWM2_CK>; |
| 161 | assigned-clocks = <&topckgen CK_TOP_PWM_SEL>, |
| 162 | <&infracfg CK_INFRA_PWM_BSEL>, |
| 163 | <&infracfg CK_INFRA_PWM1_SEL>, |
| 164 | <&infracfg CK_INFRA_PWM2_SEL>; |
| 165 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>, |
| 166 | <&infracfg CK_INFRA_PWM>, |
| 167 | <&infracfg CK_INFRA_PWM>, |
| 168 | <&infracfg CK_INFRA_PWM>; |
| 169 | clock-names = "top", "main", "pwm1", "pwm2"; |
| 170 | status = "disabled"; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 171 | bootph-all; |
developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 172 | }; |
| 173 | |
| 174 | uart0: serial@11002000 { |
| 175 | compatible = "mediatek,hsuart"; |
| 176 | reg = <0x11002000 0x400>; |
| 177 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| 178 | clocks = <&infracfg_ao CK_INFRA_UART0_CK>; |
| 179 | assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| 180 | <&infracfg_ao CK_INFRA_UART0_SEL>; |
| 181 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 182 | <&infracfg CK_INFRA_UART>; |
| 183 | mediatek,force-highspeed; |
| 184 | status = "disabled"; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 185 | bootph-all; |
developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 186 | }; |
| 187 | |
| 188 | uart1: serial@11003000 { |
| 189 | compatible = "mediatek,hsuart"; |
| 190 | reg = <0x11003000 0x400>; |
| 191 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| 192 | clocks = <&infracfg_ao CK_INFRA_UART1_CK>; |
| 193 | assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>; |
| 194 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
| 195 | mediatek,force-highspeed; |
| 196 | status = "disabled"; |
| 197 | }; |
| 198 | |
| 199 | uart2: serial@11004000 { |
| 200 | compatible = "mediatek,hsuart"; |
| 201 | reg = <0x11004000 0x400>; |
| 202 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| 203 | clocks = <&infracfg_ao CK_INFRA_UART2_CK>; |
| 204 | assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>; |
| 205 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
| 206 | mediatek,force-highspeed; |
| 207 | status = "disabled"; |
| 208 | }; |
| 209 | |
| 210 | snand: snand@11005000 { |
| 211 | compatible = "mediatek,mt7986-snand"; |
| 212 | reg = <0x11005000 0x1000>, |
| 213 | <0x11006000 0x1000>; |
| 214 | reg-names = "nfi", "ecc"; |
| 215 | clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, |
| 216 | <&infracfg_ao CK_INFRA_NFI1_CK>, |
| 217 | <&infracfg_ao CK_INFRA_NFI_HCK_CK>; |
| 218 | clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; |
| 219 | assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| 220 | <&topckgen CK_TOP_NFI1X_SEL>; |
| 221 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, |
| 222 | <&topckgen CK_TOP_CB_M_D8>; |
| 223 | status = "disabled"; |
| 224 | }; |
| 225 | |
| 226 | ethsys: syscon@15000000 { |
| 227 | compatible = "mediatek,mt7986-ethsys", "syscon"; |
| 228 | reg = <0x15000000 0x1000>; |
| 229 | clock-parent = <&topckgen>; |
| 230 | #clock-cells = <1>; |
| 231 | #reset-cells = <1>; |
| 232 | }; |
| 233 | |
| 234 | eth: ethernet@15100000 { |
| 235 | compatible = "mediatek,mt7986-eth", "syscon"; |
| 236 | reg = <0x15100000 0x20000>; |
| 237 | resets = <ðsys ETHSYS_FE_RST>; |
| 238 | reset-names = "fe"; |
| 239 | mediatek,ethsys = <ðsys>; |
| 240 | mediatek,sgmiisys = <&sgmiisys0>; |
| 241 | #address-cells = <1>; |
| 242 | #size-cells = <0>; |
| 243 | status = "disabled"; |
| 244 | }; |
| 245 | |
| 246 | sgmiisys0: syscon@10060000 { |
| 247 | compatible = "mediatek,mt7986-sgmiisys", "syscon"; |
| 248 | reg = <0x10060000 0x1000>; |
| 249 | #clock-cells = <1>; |
| 250 | }; |
| 251 | |
| 252 | sgmiisys1: syscon@10070000 { |
| 253 | compatible = "mediatek,mt7986-sgmiisys", "syscon"; |
| 254 | reg = <0x10070000 0x1000>; |
| 255 | #clock-cells = <1>; |
| 256 | }; |
| 257 | |
| 258 | spi0: spi@1100a000 { |
| 259 | compatible = "mediatek,ipm-spi"; |
| 260 | reg = <0x1100a000 0x100>; |
| 261 | clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, |
| 262 | <&topckgen CK_TOP_SPI_SEL>; |
| 263 | assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, |
| 264 | <&infracfg CK_INFRA_SPI0_SEL>; |
| 265 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, |
| 266 | <&topckgen CK_INFRA_ISPI0>; |
| 267 | clock-names = "sel-clk", "spi-clk"; |
| 268 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| 269 | status = "disabled"; |
| 270 | }; |
| 271 | |
| 272 | spi1: spi@1100b000 { |
| 273 | compatible = "mediatek,ipm-spi"; |
| 274 | reg = <0x1100b000 0x100>; |
| 275 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| 276 | status = "disabled"; |
| 277 | }; |
| 278 | |
| 279 | mmc0: mmc@11230000 { |
| 280 | compatible = "mediatek,mt7986-mmc"; |
| 281 | reg = <0x11230000 0x1000>, |
| 282 | <0x11C20000 0x1000>; |
| 283 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| 284 | clocks = <&topckgen CK_TOP_EMMC_416M>, |
| 285 | <&topckgen CK_TOP_EMMC_250M>, |
| 286 | <&infracfg_ao CK_INFRA_MSDC_CK>; |
| 287 | assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>, |
| 288 | <&topckgen CK_TOP_EMMC_250M_SEL>; |
| 289 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>, |
| 290 | <&topckgen CK_TOP_NET1_D5_D2>; |
| 291 | clock-names = "source", "hclk", "source_cg"; |
| 292 | status = "disabled"; |
| 293 | }; |
| 294 | |
| 295 | xhci: xhci@11200000 { |
| 296 | compatible = "mediatek,mt7986-xhci", |
| 297 | "mediatek,mtk-xhci"; |
| 298 | reg = <0x11200000 0x2e00>, |
| 299 | <0x11203e00 0x0100>; |
| 300 | reg-names = "mac", "ippc"; |
| 301 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 302 | phys = <&u2port0 PHY_TYPE_USB2>, |
| 303 | <&u3port0 PHY_TYPE_USB3>, |
| 304 | <&u2port1 PHY_TYPE_USB2>; |
| 305 | clocks = <&dummy_clk>, |
| 306 | <&dummy_clk>, |
| 307 | <&dummy_clk>, |
| 308 | <&dummy_clk>, |
| 309 | <&dummy_clk>; |
| 310 | clock-names = "sys_ck", |
| 311 | "xhci_ck", |
| 312 | "ref_ck", |
| 313 | "mcu_ck", |
| 314 | "dma_ck"; |
| 315 | tpl-support; |
| 316 | status = "okay"; |
| 317 | }; |
| 318 | |
| 319 | usbtphy: usb-phy@11e10000 { |
| 320 | compatible = "mediatek,mt7986", |
| 321 | "mediatek,generic-tphy-v2"; |
| 322 | #address-cells = <1>; |
| 323 | #size-cells = <1>; |
| 324 | status = "okay"; |
| 325 | |
| 326 | u2port0: usb-phy@11e10000 { |
| 327 | reg = <0x11e10000 0x700>; |
| 328 | clocks = <&dummy_clk>; |
| 329 | clock-names = "ref"; |
| 330 | #phy-cells = <1>; |
| 331 | status = "okay"; |
| 332 | }; |
| 333 | |
| 334 | u3port0: usb-phy@11e10700 { |
| 335 | reg = <0x11e10700 0x900>; |
| 336 | clocks = <&dummy_clk>; |
| 337 | clock-names = "ref"; |
| 338 | #phy-cells = <1>; |
| 339 | status = "okay"; |
| 340 | }; |
| 341 | |
| 342 | u2port1: usb-phy@11e11000 { |
| 343 | reg = <0x11e11000 0x700>; |
| 344 | clocks = <&dummy_clk>; |
| 345 | clock-names = "ref"; |
| 346 | #phy-cells = <1>; |
| 347 | status = "okay"; |
| 348 | }; |
| 349 | }; |
| 350 | }; |