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git01.mediatek.com / filogic / uboot / 1f5a510b6878e737ffd997eb8ea38e8a257cf417 / . / arch / arm / dts / k3-am654-ddr.dtsi
blob: 48698cdddc7e276b6253965a16cf36cc93745657 [file] [log] [blame]
Lokesh Vutlab50abe22018-11-02 19:51:09 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
6/ {
7 memorycontroller: memorycontroller@0298e000 {
8 compatible = "ti,am654-ddrss";
9 reg = <0x0 0x0298e000 0x0 0x200>,
10 <0x0 0x02980000 0x0 0x4000>,
11 <0x0 0x02988000 0x0 0x2000>;
12 reg-names = "ss", "ctl", "phy";
13 clocks = <&k3_clks 20 0>;
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]14 power-domains = <&k3_pds 20 TI_SCI_PD_SHARED>,
15 <&k3_pds 244 TI_SCI_PD_SHARED>;
Lokesh Vutlab50abe22018-11-02 19:51:09 +0530[diff] [blame]16 assigned-clocks = <&k3_clks 20 1>;
17 assigned-clock-rates = <DDR_PLL_FREQUENCY>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Lokesh Vutlab50abe22018-11-02 19:51:09 +0530[diff] [blame]19
James Doublesin2c85dfd12019-10-07 14:04:27 +0530[diff] [blame]20 ti,ss-reg = <
21 DDRSS_V2H_CTL_REG
22 >;
23
Lokesh Vutlab50abe22018-11-02 19:51:09 +0530[diff] [blame]24 ti,ctl-reg = <
25 DDRCTL_DFIMISC
26 DDRCTL_DFITMG0
27 DDRCTL_DFITMG1
28 DDRCTL_DFITMG2
29 DDRCTL_INIT0
30 DDRCTL_INIT1
31 DDRCTL_INIT3
32 DDRCTL_INIT4
33 DDRCTL_INIT5
34 DDRCTL_INIT6
35 DDRCTL_INIT7
36 DDRCTL_MSTR
37 DDRCTL_ODTCFG
38 DDRCTL_ODTMAP
39 DDRCTL_RANKCTL
40 DDRCTL_RFSHCTL0
41 DDRCTL_RFSHTMG
42 DDRCTL_ZQCTL0
43 DDRCTL_ZQCTL1
44 >;
45
46 ti,ctl-crc = <
47 DDRCTL_CRCPARCTL0
48 DDRCTL_CRCPARCTL1
49 DDRCTL_CRCPARCTL2
50 >;
51
52 ti,ctl-ecc = <
53 DDRCTL_ECCCFG0
54 >;
55
56 ti,ctl-map = <
57 DDRCTL_ADDRMAP0
58 DDRCTL_ADDRMAP1
59 DDRCTL_ADDRMAP2
60 DDRCTL_ADDRMAP3
61 DDRCTL_ADDRMAP4
62 DDRCTL_ADDRMAP5
63 DDRCTL_ADDRMAP6
64 DDRCTL_ADDRMAP7
65 DDRCTL_ADDRMAP8
66 DDRCTL_ADDRMAP9
67 DDRCTL_ADDRMAP10
68 DDRCTL_ADDRMAP11
69 DDRCTL_DQMAP0
70 DDRCTL_DQMAP1
71 DDRCTL_DQMAP4
72 DDRCTL_DQMAP5
73 >;
74
75 ti,ctl-pwr = <
76 DDRCTL_PWRCTL
77 >;
78
79 ti,ctl-timing = <
80 DDRCTL_DRAMTMG0
81 DDRCTL_DRAMTMG1
82 DDRCTL_DRAMTMG2
83 DDRCTL_DRAMTMG3
84 DDRCTL_DRAMTMG4
85 DDRCTL_DRAMTMG5
86 DDRCTL_DRAMTMG6
87 DDRCTL_DRAMTMG7
88 DDRCTL_DRAMTMG8
89 DDRCTL_DRAMTMG9
90 DDRCTL_DRAMTMG11
91 DDRCTL_DRAMTMG12
92 DDRCTL_DRAMTMG13
93 DDRCTL_DRAMTMG14
94 DDRCTL_DRAMTMG15
95 DDRCTL_DRAMTMG17
96 >;
97
98 ti,phy-cfg = <
99 DDRPHY_DCR
100 DDRPHY_DSGCR
101 DDRPHY_DX0GCR0
102 DDRPHY_DX0GCR1
103 DDRPHY_DX0GCR2
104 DDRPHY_DX0GCR3
105 DDRPHY_DX0GCR4
106 DDRPHY_DX0GCR5
107 DDRPHY_DX0GTR0
108 DDRPHY_DX1GCR0
109 DDRPHY_DX1GCR1
110 DDRPHY_DX1GCR2
111 DDRPHY_DX1GCR3
112 DDRPHY_DX1GCR4
113 DDRPHY_DX1GCR5
114 DDRPHY_DX1GTR0
115 DDRPHY_DX2GCR0
116 DDRPHY_DX2GCR1
117 DDRPHY_DX2GCR2
118 DDRPHY_DX2GCR3
119 DDRPHY_DX2GCR4
120 DDRPHY_DX2GCR5
121 DDRPHY_DX2GTR0
122 DDRPHY_DX3GCR0
123 DDRPHY_DX3GCR1
124 DDRPHY_DX3GCR2
125 DDRPHY_DX3GCR3
126 DDRPHY_DX3GCR4
127 DDRPHY_DX3GCR5
128 DDRPHY_DX3GTR0
129 DDRPHY_DX4GCR0
130 DDRPHY_DX4GCR1
131 DDRPHY_DX4GCR2
132 DDRPHY_DX4GCR3
133 DDRPHY_DX4GCR4
134 DDRPHY_DX4GCR5
135 DDRPHY_DX4GTR0
136 DDRPHY_DX8SL0DXCTL2
137 DDRPHY_DX8SL0IOCR
138 DDRPHY_DX8SL0PLLCR0
James Doublesin2c85dfd12019-10-07 14:04:27 +0530[diff] [blame]139 DDRPHY_DX8SL0DQSCTL
Lokesh Vutlab50abe22018-11-02 19:51:09 +0530[diff] [blame]140 DDRPHY_DX8SL1DXCTL2
141 DDRPHY_DX8SL1IOCR
142 DDRPHY_DX8SL1PLLCR0
James Doublesin2c85dfd12019-10-07 14:04:27 +0530[diff] [blame]143 DDRPHY_DX8SL1DQSCTL
Lokesh Vutlab50abe22018-11-02 19:51:09 +0530[diff] [blame]144 DDRPHY_DX8SL2DXCTL2
145 DDRPHY_DX8SL2IOCR
146 DDRPHY_DX8SL2PLLCR0
James Doublesin2c85dfd12019-10-07 14:04:27 +0530[diff] [blame]147 DDRPHY_DX8SL2DQSCTL
Lokesh Vutlab50abe22018-11-02 19:51:09 +0530[diff] [blame]148 DDRPHY_DXCCR
149 DDRPHY_ODTCR
150 DDRPHY_PGCR0
151 DDRPHY_PGCR1
152 DDRPHY_PGCR2
153 DDRPHY_PGCR3
154 DDRPHY_PGCR5
155 DDRPHY_PGCR6
156 >;
157
158 ti,phy-ctl = <
159 DDRPHY_DTCR0
160 DDRPHY_DTCR1
161 DDRPHY_MR0
162 DDRPHY_MR1
163 DDRPHY_MR2
164 DDRPHY_MR3
165 DDRPHY_MR4
166 DDRPHY_MR5
167 DDRPHY_MR6
168 DDRPHY_MR11
169 DDRPHY_MR12
170 DDRPHY_MR13
171 DDRPHY_MR14
172 DDRPHY_MR22
173 DDRPHY_PLLCR0
174 DDRPHY_VTCR0
175 >;
176
177 ti,phy-ioctl = <
James Doublesin2c85dfd12019-10-07 14:04:27 +0530[diff] [blame]178 DDRPHY_ACIOCR0
179 DDRPHY_ACIOCR3
Lokesh Vutlab50abe22018-11-02 19:51:09 +0530[diff] [blame]180 DDRPHY_ACIOCR5
181 DDRPHY_IOVCR0
182 >;
183
184 ti,phy-timing = <
185 DDRPHY_DTPR0
186 DDRPHY_DTPR1
187 DDRPHY_DTPR2
188 DDRPHY_DTPR3
189 DDRPHY_DTPR4
190 DDRPHY_DTPR5
191 DDRPHY_DTPR6
192 DDRPHY_PTR2
193 DDRPHY_PTR3
194 DDRPHY_PTR4
195 DDRPHY_PTR5
196 DDRPHY_PTR6
197 >;
198
199 ti,phy-zq = <
200 DDRPHY_ZQ0PR0
201 DDRPHY_ZQ1PR0
202 DDRPHY_ZQCR
203 >;
204 };
205};