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git01.mediatek.com / filogic / uboot / 1f5a510b6878e737ffd997eb8ea38e8a257cf417 / . / arch / arm / dts / imx8mm-kontron-osm-s.dtsi
blob: 695da2fa7c42ac76451580aad20c00b76c333028 [file] [log] [blame]
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include "imx8mm.dtsi"
8
9/ {
10 model = "Kontron OSM-S i.MX8MM (N802X SOM)";
11 compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";
12
Frieder Schrempfce3f5992023-01-09 12:42:18 +0100[diff] [blame]13 aliases {
14 rtc0 = &rv3028;
15 rtc1 = &snvs_rtc;
16 };
17
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]18 memory@40000000 {
19 device_type = "memory";
20 /*
21 * There are multiple SoM flavors with different DDR sizes.
22 * The smallest is 1GB. For larger sizes the bootloader will
23 * update the reg property.
24 */
25 reg = <0x0 0x40000000 0 0x80000000>;
26 };
27
28 chosen {
29 stdout-path = &uart3;
30 };
31};
32
33&A53_0 {
34 cpu-supply = <&reg_vdd_arm>;
35};
36
37&A53_1 {
38 cpu-supply = <&reg_vdd_arm>;
39};
40
41&A53_2 {
42 cpu-supply = <&reg_vdd_arm>;
43};
44
45&A53_3 {
46 cpu-supply = <&reg_vdd_arm>;
47};
48
49&ddrc {
50 operating-points-v2 = <&ddrc_opp_table>;
51
52 ddrc_opp_table: opp-table {
53 compatible = "operating-points-v2";
54
55 opp-100M {
56 opp-hz = /bits/ 64 <100000000>;
57 };
58
59 opp-750M {
60 opp-hz = /bits/ 64 <750000000>;
61 };
62 };
63};
64
65&ecspi1 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_ecspi1>;
68 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
69 status = "okay";
70
71 flash@0 {
72 compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
73 spi-max-frequency = <80000000>;
74 reg = <0>;
75
76 partitions {
77 compatible = "fixed-partitions";
78 #address-cells = <1>;
79 #size-cells = <1>;
80
81 partition@0 {
82 label = "u-boot";
83 reg = <0x0 0x1e0000>;
84 };
85
86 partition@1e0000 {
87 label = "env";
88 reg = <0x1e0000 0x10000>;
89 };
90
91 partition@1f0000 {
92 label = "env_redundant";
93 reg = <0x1f0000 0x10000>;
94 };
95 };
96 };
97};
98
99&i2c1 {
100 clock-frequency = <400000>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_i2c1>;
103 status = "okay";
104
105 pca9450: pmic@25 {
106 compatible = "nxp,pca9450a";
107 reg = <0x25>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_pmic>;
110 interrupt-parent = <&gpio1>;
111 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
112
113 regulators {
114 reg_vdd_soc: BUCK1 {
115 regulator-name = "+0V8_VDD_SOC (BUCK1)";
116 regulator-min-microvolt = <800000>;
117 regulator-max-microvolt = <850000>;
118 regulator-boot-on;
119 regulator-always-on;
120 regulator-ramp-delay = <3125>;
121 nxp,dvs-run-voltage = <850000>;
122 nxp,dvs-standby-voltage = <800000>;
123 };
124
125 reg_vdd_arm: BUCK2 {
126 regulator-name = "+0V9_VDD_ARM (BUCK2)";
127 regulator-min-microvolt = <850000>;
128 regulator-max-microvolt = <950000>;
129 regulator-boot-on;
130 regulator-always-on;
131 regulator-ramp-delay = <3125>;
132 nxp,dvs-run-voltage = <950000>;
133 nxp,dvs-standby-voltage = <850000>;
134 };
135
136 reg_vdd_dram: BUCK3 {
137 regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
138 regulator-min-microvolt = <850000>;
139 regulator-max-microvolt = <950000>;
140 regulator-boot-on;
141 regulator-always-on;
142 };
143
144 reg_vdd_3v3: BUCK4 {
145 regulator-name = "+3V3 (BUCK4)";
146 regulator-min-microvolt = <3300000>;
147 regulator-max-microvolt = <3300000>;
148 regulator-boot-on;
149 regulator-always-on;
150 };
151
152 reg_vdd_1v8: BUCK5 {
153 regulator-name = "+1V8 (BUCK5)";
154 regulator-min-microvolt = <1800000>;
155 regulator-max-microvolt = <1800000>;
156 regulator-boot-on;
157 regulator-always-on;
158 };
159
160 reg_nvcc_dram: BUCK6 {
161 regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
162 regulator-min-microvolt = <1100000>;
163 regulator-max-microvolt = <1100000>;
164 regulator-boot-on;
165 regulator-always-on;
166 };
167
168 reg_nvcc_snvs: LDO1 {
169 regulator-name = "+1V8_NVCC_SNVS (LDO1)";
170 regulator-min-microvolt = <1800000>;
171 regulator-max-microvolt = <1800000>;
172 regulator-boot-on;
173 regulator-always-on;
174 };
175
176 reg_vdd_snvs: LDO2 {
177 regulator-name = "+0V8_VDD_SNVS (LDO2)";
178 regulator-min-microvolt = <800000>;
179 regulator-max-microvolt = <900000>;
180 regulator-boot-on;
181 regulator-always-on;
182 };
183
184 reg_vdda: LDO3 {
185 regulator-name = "+1V8_VDDA (LDO3)";
186 regulator-min-microvolt = <1800000>;
187 regulator-max-microvolt = <1800000>;
188 regulator-boot-on;
189 regulator-always-on;
190 };
191
192 reg_vdd_phy: LDO4 {
193 regulator-name = "+0V9_VDD_PHY (LDO4)";
194 regulator-min-microvolt = <900000>;
195 regulator-max-microvolt = <900000>;
196 regulator-boot-on;
197 regulator-always-on;
198 };
199
200 reg_nvcc_sd: LDO5 {
201 regulator-name = "NVCC_SD (LDO5)";
202 regulator-min-microvolt = <1800000>;
203 regulator-max-microvolt = <3300000>;
204 };
205 };
206 };
207
Frieder Schrempfce3f5992023-01-09 12:42:18 +0100[diff] [blame]208 rv3028: rtc@52 {
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]209 compatible = "microcrystal,rv3028";
210 reg = <0x52>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_rtc>;
213 interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>;
214 trickle-diode-disable;
215 };
216};
217
218&uart3 { /* console */
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_uart3>;
221 status = "okay";
222};
223
224&usdhc1 {
225 pinctrl-names = "default", "state_100mhz", "state_200mhz";
226 pinctrl-0 = <&pinctrl_usdhc1>;
227 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
228 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
229 vmmc-supply = <&reg_vdd_3v3>;
230 vqmmc-supply = <&reg_vdd_1v8>;
231 bus-width = <8>;
232 non-removable;
233 status = "okay";
234};
235
236&wdog1 {
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_wdog>;
239 fsl,ext-reset-output;
240 status = "okay";
241};
242
243&iomuxc {
244 pinctrl_ecspi1: ecspi1grp {
245 fsl,pins = <
246 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
247 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
248 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
249 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
250 >;
251 };
252
253 pinctrl_i2c1: i2c1grp {
254 fsl,pins = <
255 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
256 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
257 >;
258 };
259
260 pinctrl_pmic: pmicgrp {
261 fsl,pins = <
262 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
263 >;
264 };
265
266 pinctrl_rtc: rtcgrp {
267 fsl,pins = <
268 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
269 >;
270 };
271
272 pinctrl_uart3: uart3grp {
273 fsl,pins = <
274 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
275 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
276 >;
277 };
278
279 pinctrl_usdhc1: usdhc1grp {
280 fsl,pins = <
281 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
282 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
283 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
284 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
285 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
286 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
287 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
288 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
289 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
290 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
291 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
292 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
293 >;
294 };
295
296 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
297 fsl,pins = <
298 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
299 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
300 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
301 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
302 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
303 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
304 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
305 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
306 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
307 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
308 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
309 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
310 >;
311 };
312
313 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
314 fsl,pins = <
315 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
316 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
317 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
318 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
319 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
320 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
321 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
322 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
323 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
324 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
325 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
326 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
327 >;
328 };
329
330 pinctrl_wdog: wdoggrp {
331 fsl,pins = <
332 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
333 >;
334 };
335};