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git01.mediatek.com / filogic / uboot / 1f5a510b6878e737ffd997eb8ea38e8a257cf417 / . / arch / arm / dts / imx8mm-kontron-bl-common-u-boot.dtsi
blob: 1ad9d49a1118d518354d4f267e5de9b4149c3590 [file] [log] [blame]
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
9 aliases {
10 usb0 = &usbotg1;
11 usb1 = &usbotg2;
12 };
13
14 wdt-reboot {
15 compatible = "wdt-reboot";
16 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]18 };
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]19};
20
21&crypto {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]23};
24
25&sec_jr0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]27};
28
29&sec_jr1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]31};
32
33&sec_jr2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]35};
36
37&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
39 bootph-all;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]40};
41
42&i2c2 {
43 status = "okay";
Frieder Schrempf26e05b32022-08-24 15:59:20 +0200[diff] [blame]44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_i2c2>;
46};
47
48&iomuxc {
49 pinctrl_i2c2: i2c2grp {
50 fsl,pins = <
51 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
52 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
53 >;
54 };
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]55};
56
57&pinctrl_ecspi1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]59};
60
61&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]63};
64
65&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]67};
68
69&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
71 bootph-all;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]72};
73
74&pinctrl_usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]76};
77
78&pinctrl_usdhc1_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]80};
81
82&pinctrl_usdhc1_200mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]84};
85
86&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]88};
89
90&pca9450 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]92};
93
94&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]96};
97
98&ecspi1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]100};
101
102&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]104};
105
106&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]108};
109
110&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]112};
113
114&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]116};
117
118&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]120};
121
122&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-pre-ram;
124 bootph-all;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]125};
126
127&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]129};
130
131&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]133};
134
135&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]137};
138
139&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]140 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]141};