Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 1f5a510b6878e737ffd997eb8ea38e8a257cf417 / . / arch / arm / dts / imx8mm-cl-iot-gate-optee-u-boot.dtsi
blob: c4327d318736972f1952ccd70dc851cefb2713dc [file] [log] [blame]
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Marcel Ziswiler9888e122021-10-23 01:15:12 +0200[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]8/ {
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]9 wdt-reboot {
10 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]11 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]12 wdt = <&wdog1>;
13 };
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]14};
15
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]16&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]18};
19
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]20&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]22};
23
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]24&binman_fip {
25 arch = "arm64";
26 compression = "none";
27 description = "Trusted Firmware FIP";
28 load = <0x40310000>;
29 type = "firmware";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]30
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]31 fip_blob {
32 filename = "fip.bin";
33 type = "blob-ext";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]34 };
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]35};
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]36
Simon Glassceea7842023-08-23 19:18:01 -0600[diff] [blame]37/* This cannot work since it refers to a template node
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]38&binman_configuration {
39 loadables = "atf", "fip";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]40};
Simon Glassceea7842023-08-23 19:18:01 -0600[diff] [blame]41*/
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]42
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]43&fec1 {
44 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
45};
46
47&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]49};
50
51&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]53};
54
55&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]57};
58
59&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]61};
62
63&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]65};
66
67&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]69};
70
71&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]73};
74
75&pinctrl_i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]77};
78
79&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]81};
82
83&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]85};
86
87&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]89};
90
91&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]93};
94
95&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]97};
98
99&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]101};
102
103&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]105};
106
107&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]109};
110
111&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]113};
114
115&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]117};