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git01.mediatek.com / filogic / uboot / 1f5a510b6878e737ffd997eb8ea38e8a257cf417 / . / arch / arm / dts / fsl-imx8qxp-ai_ml-u-boot.dtsi
blob: 79f08ec138bbf7c536ed701e3a8508e9530b8d1c [file] [log] [blame]
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Linaro Ltd.
4 */
5
6&{/imx8qx-pm} {
7
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]8 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]9};
10
11&mu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]13};
14
15&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]16 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]17};
18
19&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]21};
22
23&pd_lsio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]25};
26
27&pd_lsio_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]29};
30
31&pd_lsio_gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]33};
34
35&pd_lsio_gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]37};
38
39&pd_lsio_gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]41};
42
43&pd_lsio_gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]45};
46
47&pd_lsio_gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]49};
50
51&pd_lsio_gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]53};
54
55&pd_lsio_gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]57};
58
59&pd_conn {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]61};
62
63&pd_conn_sdch0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]65};
66
67&pd_conn_sdch1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]69};
70
71&pd_conn_sdch2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]73};
74
75&gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]77};
78
79&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]81};
82
83&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]85};
86
87&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]89};
90
91&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]93};
94
95&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]97};
98
99&gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]101};
102
103&gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]105};
106
107&lpuart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]109};
110
111&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]113};
114
115&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Manivannan Sadhasivam0b050c02019-08-15 13:57:24 +0530[diff] [blame]117};