Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2016 NXP Semiconductors |
| 4 | * Copyright (C) 2021 Fabio Estevam <festevam@denx.de> |
| 5 | * |
| 6 | * Configuration settings for the smegw01 board. |
| 7 | */ |
| 8 | |
| 9 | #ifndef __SMEGW01_CONFIG_H |
| 10 | #define __SMEGW01_CONFIG_H |
| 11 | |
| 12 | #include "mx7_common.h" |
| 13 | #include <imximage.h> |
| 14 | |
| 15 | #define PHYS_SDRAM_SIZE SZ_512M |
| 16 | |
| 17 | /* Size of malloc() pool */ |
| 18 | #define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) |
| 19 | |
| 20 | /* MMC Config*/ |
| 21 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
| 22 | #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 |
| 23 | |
| 24 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 25 | "image=zImage\0" \ |
| 26 | "console=ttymxc0\0" \ |
| 27 | "fdtfile=imx7d-smegw01.dtb\0" \ |
| 28 | "fdt_addr=0x83000000\0" \ |
| 29 | "bootm_size=0x10000000\0" \ |
| 30 | "mmcdev=0\0" \ |
| 31 | "mmcpart=1\0" \ |
Fabio Estevam | 8fd783d | 2021-06-15 20:38:38 -0300 | [diff] [blame] | 32 | "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \ |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 33 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ |
| 34 | "root=${mmcroot}\0" \ |
Fabio Estevam | 8fd783d | 2021-06-15 20:38:38 -0300 | [diff] [blame] | 35 | "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ |
| 36 | "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 37 | "mmcboot=echo Booting from mmc ...; " \ |
| 38 | "run mmcargs; " \ |
| 39 | "if run loadfdt; then " \ |
| 40 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
| 41 | "fi;\0" \ |
| 42 | |
| 43 | #define CONFIG_BOOTCOMMAND \ |
| 44 | "if run loadimage; then " \ |
| 45 | "run mmcboot; " \ |
| 46 | "fi; " \ |
| 47 | |
| 48 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 49 | #define CONFIG_SYS_HZ 1000 |
| 50 | |
| 51 | /* Physical Memory Map */ |
| 52 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
| 53 | |
| 54 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
| 55 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 56 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
| 57 | |
| 58 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 59 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 60 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 61 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 62 | |
| 63 | #endif |