blob: ff92c4f55407603e13740a431b39492b48ec6232 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Rob Herring73089ad2011-10-24 08:50:20 +00002/*
3 * Copyright 2010-2011 Calxeda, Inc.
Rob Herring73089ad2011-10-24 08:50:20 +00004 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
Rob Herring73089ad2011-10-24 08:50:20 +00009#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
10
Rob Herring8ba859a2013-10-04 10:22:43 -050011#define CONFIG_SYS_TIMER_RATE (150000000/256)
12#define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4)
13#define CONFIG_SYS_TIMER_COUNTS_DOWN
14
Rob Herring73089ad2011-10-24 08:50:20 +000015/*
16 * Size of malloc() pool
17 */
18#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
19
Rob Herring73089ad2011-10-24 08:50:20 +000020#define CONFIG_PL011_CLOCK 150000000
Rob Herring73089ad2011-10-24 08:50:20 +000021
Stefan Roese033848e2012-08-16 17:55:41 +000022#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
Rob Herring02fe7852012-02-01 16:57:54 +000023
Rob Herring73089ad2011-10-24 08:50:20 +000024#define CONFIG_SCSI_AHCI_PLAT
25#define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
26#define CONFIG_SYS_SCSI_MAX_LUN 1
27#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
28 CONFIG_SYS_SCSI_MAX_LUN)
29
Rob Herringfd5700b2013-06-12 22:24:51 -050030#define CONFIG_BOOT_RETRY_TIME -1
31#define CONFIG_RESET_TO_RETRY
Stefan Roese83da3f12015-05-18 14:08:23 +020032
Rob Herring73089ad2011-10-24 08:50:20 +000033/*
34 * Miscellaneous configurable options
35 */
Rob Herringb184c732013-06-12 22:24:47 -050036#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Rob Herring73089ad2011-10-24 08:50:20 +000037#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Rob Herring73089ad2011-10-24 08:50:20 +000038
39#define CONFIG_SYS_LOAD_ADDR 0x800000
Rob Herringb184c732013-06-12 22:24:47 -050040#define CONFIG_SYS_64BIT_LBA
41
Jason Hobbs209432a2012-02-01 16:57:56 +000042/* Environment data setup
43*/
Jason Hobbs209432a2012-02-01 16:57:56 +000044#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */
45#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
Rob Herring73089ad2011-10-24 08:50:20 +000046
47#define CONFIG_SYS_SDRAM_BASE 0x00000000
Rob Herring73089ad2011-10-24 08:50:20 +000048#define CONFIG_SYS_INIT_SP_ADDR 0x01000000
49#define CONFIG_SKIP_LOWLEVEL_INIT
50
Andre Przywara36dd0792021-04-12 01:04:50 +010051#define CONFIG_EXTRA_ENV_SETTINGS \
52 "fdt_high=0x20000000\0" \
53 "initrd_high=0x20000000\0"
54
Rob Herring73089ad2011-10-24 08:50:20 +000055#endif