Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 2 | /* |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 3 | */ |
| 4 | |
| 5 | #ifndef __AT91RM9200_H__ |
| 6 | #define __AT91RM9200_H__ |
| 7 | |
| 8 | /* Periperial Identifiers */ |
| 9 | |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 10 | #define ATMEL_ID_SYS 1 /* System Peripheral */ |
| 11 | #define ATMEL_ID_PIOA 2 /* PIO port A */ |
| 12 | #define ATMEL_ID_PIOB 3 /* PIO port B */ |
| 13 | #define ATMEL_ID_PIOC 4 /* PIO port C */ |
| 14 | #define ATMEL_ID_PIOD 5 /* PIO port D BGA only */ |
| 15 | #define ATMEL_ID_USART0 6 /* USART 0 */ |
| 16 | #define ATMEL_ID_USART1 7 /* USART 1 */ |
| 17 | #define ATMEL_ID_USART2 8 /* USART 2 */ |
| 18 | #define ATMEL_ID_USART3 9 /* USART 3 */ |
| 19 | #define ATMEL_ID_MCI 10 /* Multimedia Card Interface */ |
| 20 | #define ATMEL_ID_UDP 11 /* USB Device Port */ |
| 21 | #define ATMEL_ID_TWI 12 /* Two Wire Interface */ |
| 22 | #define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */ |
| 23 | #define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */ |
| 24 | #define ATMEL_ID_SSC1 15 /* Synch. Serial Controller 1 */ |
| 25 | #define ATMEL_ID_SSC2 16 /* Synch. Serial Controller 2 */ |
| 26 | #define ATMEL_ID_TC0 17 /* Timer Counter 0 */ |
| 27 | #define ATMEL_ID_TC1 18 /* Timer Counter 1 */ |
| 28 | #define ATMEL_ID_TC2 19 /* Timer Counter 2 */ |
| 29 | #define ATMEL_ID_TC3 20 /* Timer Counter 3 */ |
| 30 | #define ATMEL_ID_TC4 21 /* Timer Counter 4 */ |
| 31 | #define ATMEL_ID_TC5 22 /* Timer Counter 5 */ |
| 32 | #define ATMEL_ID_UHP 23 /* OHCI USB Host Port */ |
| 33 | #define ATMEL_ID_EMAC 24 /* Ethernet MAC */ |
| 34 | #define ATMEL_ID_IRQ0 25 /* Advanced Interrupt Controller */ |
| 35 | #define ATMEL_ID_IRQ1 26 /* Advanced Interrupt Controller */ |
| 36 | #define ATMEL_ID_IRQ2 27 /* Advanced Interrupt Controller */ |
| 37 | #define ATMEL_ID_IRQ3 28 /* Advanced Interrupt Controller */ |
| 38 | #define ATMEL_ID_IRQ4 29 /* Advanced Interrupt Controller */ |
| 39 | #define ATMEL_ID_IRQ5 30 /* Advanced Interrupt Controller */ |
| 40 | #define ATMEL_ID_IRQ6 31 /* Advanced Interrupt Controller */ |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 41 | |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 42 | #define ATMEL_USB_HOST_BASE 0x00300000 |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 43 | |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 44 | #define ATMEL_BASE_TC 0xFFFA0000 |
| 45 | #define ATMEL_BASE_UDP 0xFFFB0000 |
| 46 | #define ATMEL_BASE_MCI 0xFFFB4000 |
| 47 | #define ATMEL_BASE_TWI 0xFFFB8000 |
| 48 | #define ATMEL_BASE_EMAC 0xFFFBC000 |
| 49 | #define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */ |
| 50 | #define ATMEL_BASE_USART0 ATMEL_BASE_USART |
| 51 | #define ATMEL_BASE_USART1 (ATMEL_BASE_USART + 0x4000) |
| 52 | #define ATMEL_BASE_USART2 (ATMEL_BASE_USART + 0x8000) |
| 53 | #define ATMEL_BASE_USART3 (ATMEL_BASE_USART + 0xC000) |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 54 | |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 55 | #define ATMEL_BASE_SCC 0xFFFD0000 /* 4x 0x4000 Offset */ |
| 56 | #define ATMEL_BASE_SPI 0xFFFE0000 |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 57 | |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 58 | #define ATMEL_BASE_AIC 0xFFFFF000 |
| 59 | #define ATMEL_BASE_DBGU 0xFFFFF200 |
| 60 | #define ATMEL_BASE_PIO 0xFFFFF400 /* 4x 0x200 Offset */ |
Andreas Bießmann | 5e1f6c8 | 2011-06-12 01:49:13 +0000 | [diff] [blame] | 61 | #define ATMEL_BASE_PIOA 0xFFFFF400 |
| 62 | #define ATMEL_BASE_PIOB 0xFFFFF600 |
| 63 | #define ATMEL_BASE_PIOC 0xFFFFF800 |
| 64 | #define ATMEL_BASE_PIOD 0xFFFFFA00 |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 65 | #define ATMEL_BASE_PMC 0xFFFFFC00 |
| 66 | #define ATMEL_BASE_ST 0xFFFFFD00 |
| 67 | #define ATMEL_BASE_RTC 0xFFFFFE00 |
| 68 | #define ATMEL_BASE_MC 0xFFFFFF00 |
| 69 | |
| 70 | #define AT91_PIO_BASE ATMEL_BASE_PIO |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 71 | |
| 72 | /* AT91RM9200 Periperial Multiplexing A */ |
| 73 | /* Port A */ |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 74 | #define ATMEL_PMX_AA_EREFCK 0x00000080 |
| 75 | #define ATMEL_PMX_AA_ETXCK 0x00000080 |
| 76 | #define ATMEL_PMX_AA_ETXEN 0x00000100 |
| 77 | #define ATMEL_PMX_AA_ETX0 0x00000200 |
| 78 | #define ATMEL_PMX_AA_ETX1 0x00000400 |
| 79 | #define ATMEL_PMX_AA_ECRS 0x00000800 |
| 80 | #define ATMEL_PMX_AA_ECRSDV 0x00000800 |
| 81 | #define ATMEL_PMX_AA_ERX0 0x00001000 |
| 82 | #define ATMEL_PMX_AA_ERX1 0x00002000 |
| 83 | #define ATMEL_PMX_AA_ERXER 0x00004000 |
| 84 | #define ATMEL_PMX_AA_EMDC 0x00008000 |
| 85 | #define ATMEL_PMX_AA_EMDIO 0x00010000 |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 86 | |
Andreas Bießmann | 0ba0311 | 2011-06-12 01:25:16 +0000 | [diff] [blame] | 87 | #define ATMEL_PMX_AA_TXD2 0x00800000 |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 88 | |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 89 | #define ATMEL_PMX_AA_TWD 0x02000000 |
| 90 | #define ATMEL_PMX_AA_TWCK 0x04000000 |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 91 | |
| 92 | /* Port B */ |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 93 | #define ATMEL_PMX_BA_ERXCK 0x00080000 |
| 94 | #define ATMEL_PMX_BA_ECOL 0x00040000 |
| 95 | #define ATMEL_PMX_BA_ERXDV 0x00020000 |
| 96 | #define ATMEL_PMX_BA_ERX3 0x00010000 |
| 97 | #define ATMEL_PMX_BA_ERX2 0x00008000 |
| 98 | #define ATMEL_PMX_BA_ETXER 0x00004000 |
| 99 | #define ATMEL_PMX_BA_ETX3 0x00002000 |
| 100 | #define ATMEL_PMX_BA_ETX2 0x00001000 |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 101 | |
| 102 | /* Port B */ |
| 103 | |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 104 | #define ATMEL_PMX_CA_BFCK 0x00000001 |
| 105 | #define ATMEL_PMX_CA_BFRDY 0x00000002 |
| 106 | #define ATMEL_PMX_CA_SMOE 0x00000002 |
| 107 | #define ATMEL_PMX_CA_BFAVD 0x00000004 |
| 108 | #define ATMEL_PMX_CA_BFBAA 0x00000008 |
| 109 | #define ATMEL_PMX_CA_SMWE 0x00000008 |
| 110 | #define ATMEL_PMX_CA_BFOE 0x00000010 |
| 111 | #define ATMEL_PMX_CA_BFWE 0x00000020 |
| 112 | #define ATMEL_PMX_CA_NWAIT 0x00000040 |
| 113 | #define ATMEL_PMX_CA_A23 0x00000080 |
| 114 | #define ATMEL_PMX_CA_A24 0x00000100 |
| 115 | #define ATMEL_PMX_CA_A25 0x00000200 |
| 116 | #define ATMEL_PMX_CA_CFRNW 0x00000200 |
| 117 | #define ATMEL_PMX_CA_NCS4 0x00000400 |
| 118 | #define ATMEL_PMX_CA_CFCS 0x00000400 |
| 119 | #define ATMEL_PMX_CA_NCS5 0x00000800 |
| 120 | #define ATMEL_PMX_CA_CFCE1 0x00001000 |
| 121 | #define ATMEL_PMX_CA_NCS6 0x00001000 |
| 122 | #define ATMEL_PMX_CA_CFCE2 0x00002000 |
| 123 | #define ATMEL_PMX_CA_NCS7 0x00002000 |
| 124 | #define ATMEL_PMX_CA_D16_31 0xFFFF0000 |
| 125 | |
| 126 | #define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */ |
| 127 | #define ATMEL_PMC_UHP AT91RM9200_PMC_UHP |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 128 | |
Jens Scharsig | 58aa563 | 2011-02-19 06:17:02 +0000 | [diff] [blame] | 129 | #define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200" |
Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 130 | |
| 131 | #endif |