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angelo@sysam.itf11cf752015-02-12 01:39:40 +01001/*
2 * Sysam AMCORE board configuration
3 *
Angelo Dureghello3b0d5702016-09-20 17:40:03 +02004 * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
angelo@sysam.itf11cf752015-02-12 01:39:40 +01005 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __AMCORE_CONFIG_H
10#define __AMCORE_CONFIG_H
11
12#define CONFIG_AMCORE
13#define CONFIG_HOSTNAME AMCORE
14
angelo@sysam.itf11cf752015-02-12 01:39:40 +010015#define CONFIG_MCFTMR
16#define CONFIG_MCFUART
17#define CONFIG_SYS_UART_PORT 0
angelo@sysam.itf11cf752015-02-12 01:39:40 +010018#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
19
angelo@sysam.itf11cf752015-02-12 01:39:40 +010020#define CONFIG_BOOTCOMMAND "bootm ffc20000"
Angelo Dureghello3b0d5702016-09-20 17:40:03 +020021#define CONFIG_EXTRA_ENV_SETTINGS \
22 "upgrade_uboot=loady; " \
23 "protect off 0xffc00000 0xffc1ffff; " \
24 "erase 0xffc00000 0xffc1ffff; " \
25 "cp.b 0x20000 0xffc00000 ${filesize}\0" \
26 "upgrade_kernel=loady; " \
27 "erase 0xffc20000 0xffefffff; " \
28 "cp.b 0x20000 0xffc20000 ${filesize}\0" \
29 "upgrade_jffs2=loady; " \
30 "erase 0xfff00000 0xffffffff; " \
31 "cp.b 0x20000 0xfff00000 ${filesize}\0"
angelo@sysam.itf11cf752015-02-12 01:39:40 +010032
angelo@sysam.itf11cf752015-02-12 01:39:40 +010033/* undef to save memory */
34#undef CONFIG_SYS_LONGHELP
35
36#if defined(CONFIG_CMD_KGDB)
37/* Console I/O buff. size */
38#define CONFIG_SYS_CBSIZE 1024
39#else
40#define CONFIG_SYS_CBSIZE 256
41#endif
42/* Print buffer size */
43#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
44 sizeof(CONFIG_SYS_PROMPT)+16)
45/* max number of command args */
46#define CONFIG_SYS_MAXARGS 16
47/* Boot argument buffer size */
48#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
49
angelo@sysam.itf11cf752015-02-12 01:39:40 +010050#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
angelo@sysam.itf11cf752015-02-12 01:39:40 +010051#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
52
53#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
54
55#define CONFIG_SYS_MEMTEST_START 0x0
56#define CONFIG_SYS_MEMTEST_END 0x1000000
57
58#define CONFIG_SYS_HZ 1000
59
60#define CONFIG_SYS_CLK 45000000
61#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
62/* Register Base Addrs */
63#define CONFIG_SYS_MBAR 0x10000000
64/* Definitions for initial stack pointer and data area (in DPRAM) */
65#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
66/* size of internal SRAM */
67#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
68#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
69 GENERATED_GBL_DATA_SIZE)
70#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
71
72#define CONFIG_SYS_SDRAM_BASE 0x00000000
73#define CONFIG_SYS_SDRAM_SIZE 0x1000000
74#define CONFIG_SYS_FLASH_BASE 0xffc00000
75#define CONFIG_SYS_MAX_FLASH_BANKS 1
76#define CONFIG_SYS_MAX_FLASH_SECT 1024
77#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
78
79#define CONFIG_SYS_FLASH_CFI
80#define CONFIG_FLASH_CFI_DRIVER
81#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
82/* amcore design has flash data bytes wired swapped */
83#define CONFIG_SYS_WRITE_SWAPPED_DATA
84/* reserve 128-4KB */
85#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
86#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
87#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
88#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
89
angelo@sysam.itf11cf752015-02-12 01:39:40 +010090#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
91 CONFIG_SYS_MONITOR_LEN)
92#define CONFIG_ENV_SIZE 0x1000
93#define CONFIG_ENV_SECT_SIZE 0x1000
94
angelo@sysam.it6312a952015-03-29 22:54:16 +020095#define LDS_BOARD_TEXT \
96 . = DEFINED(env_offset) ? env_offset : .; \
97 common/env_embedded.o (.text*);
98
angelo@sysam.itf11cf752015-02-12 01:39:40 +010099/* memory map space for linux boot data */
100#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
101
102/*
103 * Cache Configuration
104 *
105 * Special 8K version 3 core cache.
106 * This is a single unified instruction/data cache.
107 * sdram - single region - no masks
108 */
109#define CONFIG_SYS_CACHELINE_SIZE 16
110
111#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
112 CONFIG_SYS_INIT_RAM_SIZE - 8)
113#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
114 CONFIG_SYS_INIT_RAM_SIZE - 4)
115#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
116#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
117 CF_ACR_EN)
118#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
119 CF_CACR_EC)
120
121/* CS0 - AMD Flash, address 0xffc00000 */
122#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
123/* 4MB, AA=0,V=1 C/I BIT for errata */
124#define CONFIG_SYS_CS0_MASK 0x003f0001
125/* WS=10, AA=1, PS=16bit (10) */
126#define CONFIG_SYS_CS0_CTRL 0x1980
127/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
128#define CONFIG_SYS_CS1_BASE 0x3000
129#define CONFIG_SYS_CS1_MASK 0x00070001
130#define CONFIG_SYS_CS1_CTRL 0x0100
131
132#endif /* __AMCORE_CONFIG_H */
133