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git01.mediatek.com / filogic / uboot / 1f29ce54b3971bff9e2313e9a5fe3dda2c9e1fdc / . / arch / arm / dts / imx6ul.dtsi
blob: d5ce3f13c241c953fb8da4d1fc5a8a058859f2d6 [file] [log] [blame]
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6ul-pinfunc.h"
14#include "skeleton.dtsi"
15
16/ {
17 aliases {
18 ethernet0 = &fec1;
19 ethernet1 = &fec2;
20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
24 gpio4 = &gpio5;
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 serial5 = &uart6;
37 serial6 = &uart7;
38 serial7 = &uart8;
39 sai1 = &sai1;
40 sai2 = &sai2;
41 sai3 = &sai3;
42 spi0 = &ecspi1;
43 spi1 = &ecspi2;
44 spi2 = &ecspi3;
45 spi3 = &ecspi4;
Sébastien Szymanski84646a72017-02-22 15:38:44 +0100[diff] [blame]46 usbotg0 = &usbotg1;
47 usbotg1 = &usbotg2;
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]48 usbphy0 = &usbphy1;
49 usbphy1 = &usbphy2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 cpu0: cpu@0 {
57 compatible = "arm,cortex-a7";
58 device_type = "cpu";
59 reg = <0>;
60 clock-latency = <61036>; /* two CLK32 periods */
61 operating-points = <
62 /* kHz uV */
63 528000 1175000
64 396000 1025000
65 198000 950000
66 >;
67 fsl,soc-operating-points = <
68 /* KHz uV */
69 528000 1175000
70 396000 1175000
71 198000 1175000
72 >;
73 clocks = <&clks IMX6UL_CLK_ARM>,
74 <&clks IMX6UL_CLK_PLL2_BUS>,
75 <&clks IMX6UL_CLK_PLL2_PFD2>,
76 <&clks IMX6UL_CA7_SECONDARY_SEL>,
77 <&clks IMX6UL_CLK_STEP>,
78 <&clks IMX6UL_CLK_PLL1_SW>,
79 <&clks IMX6UL_CLK_PLL1_SYS>,
80 <&clks IMX6UL_PLL1_BYPASS>,
81 <&clks IMX6UL_CLK_PLL1>,
82 <&clks IMX6UL_PLL1_BYPASS_SRC>,
83 <&clks IMX6UL_CLK_OSC>;
84 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
85 "secondary_sel", "step", "pll1_sw",
86 "pll1_sys", "pll1_bypass", "pll1",
87 "pll1_bypass_src", "osc";
88 arm-supply = <&reg_arm>;
89 soc-supply = <&reg_soc>;
90 };
91 };
92
93 intc: interrupt-controller@00a01000 {
94 compatible = "arm,cortex-a7-gic";
95 #interrupt-cells = <3>;
96 interrupt-controller;
97 reg = <0x00a01000 0x1000>,
98 <0x00a02000 0x1000>,
99 <0x00a04000 0x2000>,
100 <0x00a06000 0x2000>;
101 };
102
103 ckil: clock-cli {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <32768>;
107 clock-output-names = "ckil";
108 };
109
110 osc: clock-osc {
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <24000000>;
114 clock-output-names = "osc";
115 };
116
117 ipp_di0: clock-di0 {
118 compatible = "fixed-clock";
119 #clock-cells = <0>;
120 clock-frequency = <0>;
121 clock-output-names = "ipp_di0";
122 };
123
124 ipp_di1: clock-di1 {
125 compatible = "fixed-clock";
126 #clock-cells = <0>;
127 clock-frequency = <0>;
128 clock-output-names = "ipp_di1";
129 };
130
131 soc {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "simple-bus";
135 interrupt-parent = <&gpc>;
136 ranges;
Jagan Tekifbd71f82017-11-21 00:02:14 +0530[diff] [blame]137 u-boot,dm-spl;
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]138
139 pmu {
140 compatible = "arm,cortex-a7-pmu";
141 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
142 status = "disabled";
143 };
144
145 ocram: sram@00900000 {
146 compatible = "mmio-sram";
147 reg = <0x00900000 0x20000>;
148 };
149
150 dma_apbh: dma-apbh@01804000 {
151 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
152 reg = <0x01804000 0x2000>;
153 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
154 <0 13 IRQ_TYPE_LEVEL_HIGH>,
155 <0 13 IRQ_TYPE_LEVEL_HIGH>,
156 <0 13 IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
158 #dma-cells = <1>;
159 dma-channels = <4>;
160 clocks = <&clks IMX6UL_CLK_APBHDMA>;
161 };
162
163 gpmi: gpmi-nand@01806000 {
164 compatible = "fsl,imx6q-gpmi-nand";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
168 reg-names = "gpmi-nand", "bch";
169 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-names = "bch";
171 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
172 <&clks IMX6UL_CLK_GPMI_APB>,
173 <&clks IMX6UL_CLK_GPMI_BCH>,
174 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
175 <&clks IMX6UL_CLK_PER_BCH>;
176 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
177 "gpmi_bch_apb", "per1_bch";
178 dmas = <&dma_apbh 0>;
179 dma-names = "rx-tx";
180 status = "disabled";
181 };
182
183 aips1: aips-bus@02000000 {
184 compatible = "fsl,aips-bus", "simple-bus";
185 #address-cells = <1>;
186 #size-cells = <1>;
187 reg = <0x02000000 0x100000>;
188 ranges;
Jagan Tekifbd71f82017-11-21 00:02:14 +0530[diff] [blame]189 u-boot,dm-spl;
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]190
191 spba-bus@02000000 {
192 compatible = "fsl,spba-bus", "simple-bus";
193 #address-cells = <1>;
194 #size-cells = <1>;
195 reg = <0x02000000 0x40000>;
196 ranges;
Sébastien Szymanski1f29ce52018-04-17 17:29:31 +0200[diff] [blame^]197 u-boot,dm-spl;
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]198
199 ecspi1: ecspi@02008000 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
203 reg = <0x02008000 0x4000>;
204 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6UL_CLK_ECSPI1>,
206 <&clks IMX6UL_CLK_ECSPI1>;
207 clock-names = "ipg", "per";
208 status = "disabled";
209 };
210
211 ecspi2: ecspi@0200c000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
215 reg = <0x0200c000 0x4000>;
216 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clks IMX6UL_CLK_ECSPI2>,
218 <&clks IMX6UL_CLK_ECSPI2>;
219 clock-names = "ipg", "per";
220 status = "disabled";
221 };
222
223 ecspi3: ecspi@02010000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
227 reg = <0x02010000 0x4000>;
228 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&clks IMX6UL_CLK_ECSPI3>,
230 <&clks IMX6UL_CLK_ECSPI3>;
231 clock-names = "ipg", "per";
232 status = "disabled";
233 };
234
235 ecspi4: ecspi@02014000 {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
239 reg = <0x02014000 0x4000>;
240 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clks IMX6UL_CLK_ECSPI4>,
242 <&clks IMX6UL_CLK_ECSPI4>;
243 clock-names = "ipg", "per";
244 status = "disabled";
245 };
246
247 uart7: serial@02018000 {
248 compatible = "fsl,imx6ul-uart",
249 "fsl,imx6q-uart";
250 reg = <0x02018000 0x4000>;
251 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
253 <&clks IMX6UL_CLK_UART7_SERIAL>;
254 clock-names = "ipg", "per";
255 status = "disabled";
256 };
257
258 uart1: serial@02020000 {
259 compatible = "fsl,imx6ul-uart",
260 "fsl,imx6q-uart";
261 reg = <0x02020000 0x4000>;
262 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
264 <&clks IMX6UL_CLK_UART1_SERIAL>;
265 clock-names = "ipg", "per";
266 status = "disabled";
267 };
268
269 uart8: serial@02024000 {
270 compatible = "fsl,imx6ul-uart",
271 "fsl,imx6q-uart";
272 reg = <0x02024000 0x4000>;
273 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
275 <&clks IMX6UL_CLK_UART8_SERIAL>;
276 clock-names = "ipg", "per";
277 status = "disabled";
278 };
279
280 sai1: sai@02028000 {
281 #sound-dai-cells = <0>;
282 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
283 reg = <0x02028000 0x4000>;
284 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
286 <&clks IMX6UL_CLK_SAI1>,
287 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
288 clock-names = "bus", "mclk1", "mclk2", "mclk3";
289 dmas = <&sdma 35 24 0>,
290 <&sdma 36 24 0>;
291 dma-names = "rx", "tx";
292 status = "disabled";
293 };
294
295 sai2: sai@0202c000 {
296 #sound-dai-cells = <0>;
297 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
298 reg = <0x0202c000 0x4000>;
299 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
301 <&clks IMX6UL_CLK_SAI2>,
302 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
303 clock-names = "bus", "mclk1", "mclk2", "mclk3";
304 dmas = <&sdma 37 24 0>,
305 <&sdma 38 24 0>;
306 dma-names = "rx", "tx";
307 status = "disabled";
308 };
309
310 sai3: sai@02030000 {
311 #sound-dai-cells = <0>;
312 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
313 reg = <0x02030000 0x4000>;
314 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
316 <&clks IMX6UL_CLK_SAI3>,
317 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
318 clock-names = "bus", "mclk1", "mclk2", "mclk3";
319 dmas = <&sdma 39 24 0>,
320 <&sdma 40 24 0>;
321 dma-names = "rx", "tx";
322 status = "disabled";
323 };
324 };
325
326 tsc: tsc@02040000 {
327 compatible = "fsl,imx6ul-tsc";
328 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
329 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&clks IMX6UL_CLK_IPG>,
332 <&clks IMX6UL_CLK_ADC2>;
333 clock-names = "tsc", "adc";
334 status = "disabled";
335 };
336
337 pwm1: pwm@02080000 {
338 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
339 reg = <0x02080000 0x4000>;
340 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clks IMX6UL_CLK_PWM1>,
342 <&clks IMX6UL_CLK_PWM1>;
343 clock-names = "ipg", "per";
344 #pwm-cells = <2>;
345 status = "disabled";
346 };
347
348 pwm2: pwm@02084000 {
349 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
350 reg = <0x02084000 0x4000>;
351 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&clks IMX6UL_CLK_PWM2>,
353 <&clks IMX6UL_CLK_PWM2>;
354 clock-names = "ipg", "per";
355 #pwm-cells = <2>;
356 status = "disabled";
357 };
358
359 pwm3: pwm@02088000 {
360 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
361 reg = <0x02088000 0x4000>;
362 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clks IMX6UL_CLK_PWM3>,
364 <&clks IMX6UL_CLK_PWM3>;
365 clock-names = "ipg", "per";
366 #pwm-cells = <2>;
367 status = "disabled";
368 };
369
370 pwm4: pwm@0208c000 {
371 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
372 reg = <0x0208c000 0x4000>;
373 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&clks IMX6UL_CLK_PWM4>,
375 <&clks IMX6UL_CLK_PWM4>;
376 clock-names = "ipg", "per";
377 #pwm-cells = <2>;
378 status = "disabled";
379 };
380
381 can1: flexcan@02090000 {
382 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
383 reg = <0x02090000 0x4000>;
384 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
386 <&clks IMX6UL_CLK_CAN1_SERIAL>;
387 clock-names = "ipg", "per";
388 status = "disabled";
389 };
390
391 can2: flexcan@02094000 {
392 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
393 reg = <0x02094000 0x4000>;
394 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
396 <&clks IMX6UL_CLK_CAN2_SERIAL>;
397 clock-names = "ipg", "per";
398 status = "disabled";
399 };
400
401 gpt1: gpt@02098000 {
402 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
403 reg = <0x02098000 0x4000>;
404 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
406 <&clks IMX6UL_CLK_GPT1_SERIAL>;
407 clock-names = "ipg", "per";
408 };
409
410 gpio1: gpio@0209c000 {
411 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
412 reg = <0x0209c000 0x4000>;
413 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
415 gpio-controller;
416 #gpio-cells = <2>;
417 interrupt-controller;
418 #interrupt-cells = <2>;
419 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
420 <&iomuxc 16 33 16>;
Jagan Tekifbd71f82017-11-21 00:02:14 +0530[diff] [blame]421 u-boot,dm-spl;
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]422 };
423
424 gpio2: gpio@020a0000 {
425 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
426 reg = <0x020a0000 0x4000>;
427 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
429 gpio-controller;
430 #gpio-cells = <2>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
434 };
435
436 gpio3: gpio@020a4000 {
437 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
438 reg = <0x020a4000 0x4000>;
439 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
441 gpio-controller;
442 #gpio-cells = <2>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
445 gpio-ranges = <&iomuxc 0 65 29>;
446 };
447
448 gpio4: gpio@020a8000 {
449 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
450 reg = <0x020a8000 0x4000>;
451 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
453 gpio-controller;
454 #gpio-cells = <2>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
Jagan Tekifbd71f82017-11-21 00:02:14 +0530[diff] [blame]458 u-boot,dm-spl;
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]459 };
460
461 gpio5: gpio@020ac000 {
462 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
463 reg = <0x020ac000 0x4000>;
464 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
466 gpio-controller;
467 #gpio-cells = <2>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
471 };
472
473 fec2: ethernet@020b4000 {
474 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
475 reg = <0x020b4000 0x4000>;
476 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&clks IMX6UL_CLK_ENET>,
479 <&clks IMX6UL_CLK_ENET_AHB>,
480 <&clks IMX6UL_CLK_ENET_PTP>,
481 <&clks IMX6UL_CLK_ENET2_REF_125M>,
482 <&clks IMX6UL_CLK_ENET2_REF_125M>;
483 clock-names = "ipg", "ahb", "ptp",
484 "enet_clk_ref", "enet_out";
485 fsl,num-tx-queues=<1>;
486 fsl,num-rx-queues=<1>;
487 status = "disabled";
488 };
489
490 kpp: kpp@020b8000 {
491 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
492 reg = <0x020b8000 0x4000>;
493 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clks IMX6UL_CLK_KPP>;
495 status = "disabled";
496 };
497
498 wdog1: wdog@020bc000 {
499 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
500 reg = <0x020bc000 0x4000>;
501 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clks IMX6UL_CLK_WDOG1>;
503 };
504
505 wdog2: wdog@020c0000 {
506 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
507 reg = <0x020c0000 0x4000>;
508 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clks IMX6UL_CLK_WDOG2>;
510 status = "disabled";
511 };
512
513 clks: ccm@020c4000 {
514 compatible = "fsl,imx6ul-ccm";
515 reg = <0x020c4000 0x4000>;
516 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
518 #clock-cells = <1>;
519 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
520 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
521 };
522
523 anatop: anatop@020c8000 {
524 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
525 "syscon", "simple-bus";
526 reg = <0x020c8000 0x1000>;
527 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
530
531 reg_3p0: regulator-3p0 {
532 compatible = "fsl,anatop-regulator";
533 regulator-name = "vdd3p0";
534 regulator-min-microvolt = <2625000>;
535 regulator-max-microvolt = <3400000>;
536 anatop-reg-offset = <0x120>;
537 anatop-vol-bit-shift = <8>;
538 anatop-vol-bit-width = <5>;
539 anatop-min-bit-val = <0>;
540 anatop-min-voltage = <2625000>;
541 anatop-max-voltage = <3400000>;
542 anatop-enable-bit = <0>;
543 };
544
545 reg_arm: regulator-vddcore {
546 compatible = "fsl,anatop-regulator";
547 regulator-name = "cpu";
548 regulator-min-microvolt = <725000>;
549 regulator-max-microvolt = <1450000>;
550 regulator-always-on;
551 anatop-reg-offset = <0x140>;
552 anatop-vol-bit-shift = <0>;
553 anatop-vol-bit-width = <5>;
554 anatop-delay-reg-offset = <0x170>;
555 anatop-delay-bit-shift = <24>;
556 anatop-delay-bit-width = <2>;
557 anatop-min-bit-val = <1>;
558 anatop-min-voltage = <725000>;
559 anatop-max-voltage = <1450000>;
560 };
561
562 reg_soc: regulator-vddsoc {
563 compatible = "fsl,anatop-regulator";
564 regulator-name = "vddsoc";
565 regulator-min-microvolt = <725000>;
566 regulator-max-microvolt = <1450000>;
567 regulator-always-on;
568 anatop-reg-offset = <0x140>;
569 anatop-vol-bit-shift = <18>;
570 anatop-vol-bit-width = <5>;
571 anatop-delay-reg-offset = <0x170>;
572 anatop-delay-bit-shift = <28>;
573 anatop-delay-bit-width = <2>;
574 anatop-min-bit-val = <1>;
575 anatop-min-voltage = <725000>;
576 anatop-max-voltage = <1450000>;
577 };
578 };
579
580 usbphy1: usbphy@020c9000 {
581 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
582 reg = <0x020c9000 0x1000>;
583 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&clks IMX6UL_CLK_USBPHY1>;
585 phy-3p0-supply = <&reg_3p0>;
586 fsl,anatop = <&anatop>;
587 };
588
589 usbphy2: usbphy@020ca000 {
590 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
591 reg = <0x020ca000 0x1000>;
592 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&clks IMX6UL_CLK_USBPHY2>;
594 phy-3p0-supply = <&reg_3p0>;
595 fsl,anatop = <&anatop>;
596 };
597
598 snvs: snvs@020cc000 {
599 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
600 reg = <0x020cc000 0x4000>;
601
602 snvs_rtc: snvs-rtc-lp {
603 compatible = "fsl,sec-v4.0-mon-rtc-lp";
604 regmap = <&snvs>;
605 offset = <0x34>;
606 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
608 };
609
610 snvs_poweroff: snvs-poweroff {
611 compatible = "syscon-poweroff";
612 regmap = <&snvs>;
613 offset = <0x38>;
614 mask = <0x60>;
615 status = "disabled";
616 };
617
618 snvs_pwrkey: snvs-powerkey {
619 compatible = "fsl,sec-v4.0-pwrkey";
620 regmap = <&snvs>;
621 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
622 linux,keycode = <KEY_POWER>;
623 wakeup-source;
624 };
625 };
626
627 epit1: epit@020d0000 {
628 reg = <0x020d0000 0x4000>;
629 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
630 };
631
632 epit2: epit@020d4000 {
633 reg = <0x020d4000 0x4000>;
634 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
635 };
636
637 src: src@020d8000 {
638 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
639 reg = <0x020d8000 0x4000>;
640 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
642 #reset-cells = <1>;
643 };
644
645 gpc: gpc@020dc000 {
646 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
647 reg = <0x020dc000 0x4000>;
648 interrupt-controller;
649 #interrupt-cells = <3>;
650 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
651 interrupt-parent = <&intc>;
652 };
653
654 iomuxc: iomuxc@020e0000 {
655 compatible = "fsl,imx6ul-iomuxc";
656 reg = <0x020e0000 0x4000>;
Jagan Tekifbd71f82017-11-21 00:02:14 +0530[diff] [blame]657 u-boot,dm-spl;
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]658 };
659
660 gpr: iomuxc-gpr@020e4000 {
661 compatible = "fsl,imx6ul-iomuxc-gpr",
662 "fsl,imx6q-iomuxc-gpr", "syscon";
663 reg = <0x020e4000 0x4000>;
664 };
665
666 gpt2: gpt@020e8000 {
667 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
668 reg = <0x020e8000 0x4000>;
669 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
671 <&clks IMX6UL_CLK_GPT2_SERIAL>;
672 clock-names = "ipg", "per";
673 };
674
675 sdma: sdma@020ec000 {
676 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
677 "fsl,imx35-sdma";
678 reg = <0x020ec000 0x4000>;
679 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clks IMX6UL_CLK_SDMA>,
681 <&clks IMX6UL_CLK_SDMA>;
682 clock-names = "ipg", "ahb";
683 #dma-cells = <3>;
684 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
685 };
686
687 pwm5: pwm@020f0000 {
688 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
689 reg = <0x020f0000 0x4000>;
690 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clks IMX6UL_CLK_PWM5>,
692 <&clks IMX6UL_CLK_PWM5>;
693 clock-names = "ipg", "per";
694 #pwm-cells = <2>;
695 status = "disabled";
696 };
697
698 pwm6: pwm@020f4000 {
699 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
700 reg = <0x020f4000 0x4000>;
701 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&clks IMX6UL_CLK_PWM6>,
703 <&clks IMX6UL_CLK_PWM6>;
704 clock-names = "ipg", "per";
705 #pwm-cells = <2>;
706 status = "disabled";
707 };
708
709 pwm7: pwm@020f8000 {
710 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
711 reg = <0x020f8000 0x4000>;
712 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clks IMX6UL_CLK_PWM7>,
714 <&clks IMX6UL_CLK_PWM7>;
715 clock-names = "ipg", "per";
716 #pwm-cells = <2>;
717 status = "disabled";
718 };
719
720 pwm8: pwm@020fc000 {
721 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
722 reg = <0x020fc000 0x4000>;
723 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&clks IMX6UL_CLK_PWM8>,
725 <&clks IMX6UL_CLK_PWM8>;
726 clock-names = "ipg", "per";
727 #pwm-cells = <2>;
728 status = "disabled";
729 };
730 };
731
732 aips2: aips-bus@02100000 {
733 compatible = "fsl,aips-bus", "simple-bus";
734 #address-cells = <1>;
735 #size-cells = <1>;
736 reg = <0x02100000 0x100000>;
737 ranges;
Jagan Tekifbd71f82017-11-21 00:02:14 +0530[diff] [blame]738 u-boot,dm-spl;
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]739
740 usbotg1: usb@02184000 {
741 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
742 reg = <0x02184000 0x200>;
743 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clks IMX6UL_CLK_USBOH3>;
745 fsl,usbphy = <&usbphy1>;
746 fsl,usbmisc = <&usbmisc 0>;
747 fsl,anatop = <&anatop>;
748 ahb-burst-config = <0x0>;
749 tx-burst-size-dword = <0x10>;
750 rx-burst-size-dword = <0x10>;
751 status = "disabled";
752 };
753
754 usbotg2: usb@02184200 {
755 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
756 reg = <0x02184200 0x200>;
757 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&clks IMX6UL_CLK_USBOH3>;
759 fsl,usbphy = <&usbphy2>;
760 fsl,usbmisc = <&usbmisc 1>;
761 ahb-burst-config = <0x0>;
762 tx-burst-size-dword = <0x10>;
763 rx-burst-size-dword = <0x10>;
764 status = "disabled";
765 };
766
767 usbmisc: usbmisc@02184800 {
768 #index-cells = <1>;
769 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
770 reg = <0x02184800 0x200>;
771 };
772
773 fec1: ethernet@02188000 {
774 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
775 reg = <0x02188000 0x4000>;
776 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&clks IMX6UL_CLK_ENET>,
779 <&clks IMX6UL_CLK_ENET_AHB>,
780 <&clks IMX6UL_CLK_ENET_PTP>,
781 <&clks IMX6UL_CLK_ENET_REF>,
782 <&clks IMX6UL_CLK_ENET_REF>;
783 clock-names = "ipg", "ahb", "ptp",
784 "enet_clk_ref", "enet_out";
785 fsl,num-tx-queues=<1>;
786 fsl,num-rx-queues=<1>;
787 status = "disabled";
788 };
789
790 usdhc1: usdhc@02190000 {
791 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
792 reg = <0x02190000 0x4000>;
793 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&clks IMX6UL_CLK_USDHC1>,
795 <&clks IMX6UL_CLK_USDHC1>,
796 <&clks IMX6UL_CLK_USDHC1>;
797 clock-names = "ipg", "ahb", "per";
798 bus-width = <4>;
799 status = "disabled";
800 };
801
802 usdhc2: usdhc@02194000 {
803 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
804 reg = <0x02194000 0x4000>;
805 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks IMX6UL_CLK_USDHC2>,
807 <&clks IMX6UL_CLK_USDHC2>,
808 <&clks IMX6UL_CLK_USDHC2>;
809 clock-names = "ipg", "ahb", "per";
810 bus-width = <4>;
811 status = "disabled";
812 };
813
814 adc1: adc@02198000 {
815 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
816 reg = <0x02198000 0x4000>;
817 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&clks IMX6UL_CLK_ADC1>;
819 num-channels = <2>;
820 clock-names = "adc";
821 fsl,adck-max-frequency = <30000000>, <40000000>,
822 <20000000>;
823 status = "disabled";
824 };
825
826 i2c1: i2c@021a0000 {
827 #address-cells = <1>;
828 #size-cells = <0>;
829 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
830 reg = <0x021a0000 0x4000>;
831 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&clks IMX6UL_CLK_I2C1>;
833 status = "disabled";
834 };
835
836 i2c2: i2c@021a4000 {
837 #address-cells = <1>;
838 #size-cells = <0>;
839 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
840 reg = <0x021a4000 0x4000>;
841 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&clks IMX6UL_CLK_I2C2>;
843 status = "disabled";
844 };
845
846 i2c3: i2c@021a8000 {
847 #address-cells = <1>;
848 #size-cells = <0>;
849 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
850 reg = <0x021a8000 0x4000>;
851 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&clks IMX6UL_CLK_I2C3>;
853 status = "disabled";
854 };
855
856 mmdc: mmdc@021b0000 {
857 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
858 reg = <0x021b0000 0x4000>;
859 };
860
861 lcdif: lcdif@021c8000 {
862 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
863 reg = <0x021c8000 0x4000>;
864 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
866 <&clks IMX6UL_CLK_LCDIF_APB>,
867 <&clks IMX6UL_CLK_DUMMY>;
868 clock-names = "pix", "axi", "disp_axi";
869 status = "disabled";
870 };
871
872 qspi: qspi@021e0000 {
873 #address-cells = <1>;
874 #size-cells = <0>;
875 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
876 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
877 reg-names = "QuadSPI", "QuadSPI-memory";
878 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clks IMX6UL_CLK_QSPI>,
880 <&clks IMX6UL_CLK_QSPI>;
881 clock-names = "qspi_en", "qspi";
882 status = "disabled";
883 };
884
Jörg Krause533023c2018-02-25 18:12:47 +0100[diff] [blame]885 wdog3: wdog@021e4000 {
886 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
887 reg = <0x021e4000 0x4000>;
888 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&clks IMX6UL_CLK_WDOG3>;
890 status = "disabled";
891 };
892
Jagan Teki51f29192016-12-13 17:56:51 +0100[diff] [blame]893 uart2: serial@021e8000 {
894 compatible = "fsl,imx6ul-uart",
895 "fsl,imx6q-uart";
896 reg = <0x021e8000 0x4000>;
897 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
899 <&clks IMX6UL_CLK_UART2_SERIAL>;
900 clock-names = "ipg", "per";
901 status = "disabled";
902 };
903
904 uart3: serial@021ec000 {
905 compatible = "fsl,imx6ul-uart",
906 "fsl,imx6q-uart";
907 reg = <0x021ec000 0x4000>;
908 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
910 <&clks IMX6UL_CLK_UART3_SERIAL>;
911 clock-names = "ipg", "per";
912 status = "disabled";
913 };
914
915 uart4: serial@021f0000 {
916 compatible = "fsl,imx6ul-uart",
917 "fsl,imx6q-uart";
918 reg = <0x021f0000 0x4000>;
919 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
921 <&clks IMX6UL_CLK_UART4_SERIAL>;
922 clock-names = "ipg", "per";
923 status = "disabled";
924 };
925
926 uart5: serial@021f4000 {
927 compatible = "fsl,imx6ul-uart",
928 "fsl,imx6q-uart";
929 reg = <0x021f4000 0x4000>;
930 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
932 <&clks IMX6UL_CLK_UART5_SERIAL>;
933 clock-names = "ipg", "per";
934 status = "disabled";
935 };
936
937 i2c4: i2c@021f8000 {
938 #address-cells = <1>;
939 #size-cells = <0>;
940 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
941 reg = <0x021f8000 0x4000>;
942 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&clks IMX6UL_CLK_I2C4>;
944 status = "disabled";
945 };
946
947 uart6: serial@021fc000 {
948 compatible = "fsl,imx6ul-uart",
949 "fsl,imx6q-uart";
950 reg = <0x021fc000 0x4000>;
951 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
953 <&clks IMX6UL_CLK_UART6_SERIAL>;
954 clock-names = "ipg", "per";
955 status = "disabled";
956 };
957 };
958 };
959};