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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chin Liang Seecca9f452013-12-30 18:26:14 -06002/*
3 * (C) Copyright 2013 Altera Corporation <www.altera.com>
Chin Liang Seecca9f452013-12-30 18:26:14 -06004 */
5
6#include <common.h>
Chin Liang Seecca9f452013-12-30 18:26:14 -06007#include <asm/arch/clock_manager.h>
8#include <asm/arch/system_manager.h>
Marek Vasut26608602018-08-01 18:28:35 +02009#include <clk.h>
Marek Vasutae66f3c2015-11-30 20:41:04 +010010#include <dm.h>
11#include <dwmmc.h>
12#include <errno.h>
13#include <fdtdec.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090014#include <linux/libfdt.h>
Marek Vasutae66f3c2015-11-30 20:41:04 +010015#include <linux/err.h>
16#include <malloc.h>
Ley Foon Tan5a694d02018-06-14 18:45:21 +080017#include <reset.h>
Marek Vasutae66f3c2015-11-30 20:41:04 +010018
19DECLARE_GLOBAL_DATA_PTR;
Chin Liang Seecca9f452013-12-30 18:26:14 -060020
Simon Glassa3a43202016-07-05 17:10:16 -060021struct socfpga_dwmci_plat {
22 struct mmc_config cfg;
23 struct mmc mmc;
24};
25
Marek Vasutae66f3c2015-11-30 20:41:04 +010026/* socfpga implmentation specific driver private data */
Chin Liang See48e7bf92015-11-26 09:43:43 +080027struct dwmci_socfpga_priv_data {
Marek Vasutae66f3c2015-11-30 20:41:04 +010028 struct dwmci_host host;
29 unsigned int drvsel;
30 unsigned int smplsel;
Chin Liang See48e7bf92015-11-26 09:43:43 +080031};
32
Ley Foon Tan5a694d02018-06-14 18:45:21 +080033static void socfpga_dwmci_reset(struct udevice *dev)
34{
35 struct reset_ctl_bulk reset_bulk;
36 int ret;
37
38 ret = reset_get_bulk(dev, &reset_bulk);
39 if (ret) {
40 dev_warn(dev, "Can't get reset: %d\n", ret);
41 return;
42 }
43
44 reset_deassert_bulk(&reset_bulk);
45}
46
Chin Liang See48e7bf92015-11-26 09:43:43 +080047static void socfpga_dwmci_clksel(struct dwmci_host *host)
48{
49 struct dwmci_socfpga_priv_data *priv = host->priv;
Dinh Nguyenc4b66c42015-12-02 13:31:33 -060050 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
51 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
Chin Liang Seecca9f452013-12-30 18:26:14 -060052
53 /* Disable SDMMC clock. */
Ley Foon Tan26695912019-11-08 10:38:21 +080054 clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
55 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
Chin Liang Seecca9f452013-12-30 18:26:14 -060056
Chin Liang See48e7bf92015-11-26 09:43:43 +080057 debug("%s: drvsel %d smplsel %d\n", __func__,
58 priv->drvsel, priv->smplsel);
Ley Foon Tan3d3a8602019-11-08 10:38:20 +080059 writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
Chin Liang Seecca9f452013-12-30 18:26:14 -060060
61 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
Ley Foon Tan3d3a8602019-11-08 10:38:20 +080062 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
Chin Liang Seecca9f452013-12-30 18:26:14 -060063
64 /* Enable SDMMC clock */
Ley Foon Tan26695912019-11-08 10:38:21 +080065 setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
66 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
Chin Liang Seecca9f452013-12-30 18:26:14 -060067}
68
Marek Vasut26608602018-08-01 18:28:35 +020069static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
Chin Liang Seecca9f452013-12-30 18:26:14 -060070{
Marek Vasutae66f3c2015-11-30 20:41:04 +010071 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
72 struct dwmci_host *host = &priv->host;
Marek Vasut26608602018-08-01 18:28:35 +020073#if CONFIG_IS_ENABLED(CLK)
74 struct clk clk;
75 int ret;
76
77 ret = clk_get_by_index(dev, 1, &clk);
78 if (ret)
79 return ret;
80
81 host->bus_hz = clk_get_rate(&clk);
Pavel Machek51d21132014-09-08 14:08:45 +020082
Marek Vasut26608602018-08-01 18:28:35 +020083 clk_free(&clk);
84#else
85 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
86 host->bus_hz = cm_get_mmc_controller_clk_hz();
87#endif
88 if (host->bus_hz == 0) {
Marek Vasutae66f3c2015-11-30 20:41:04 +010089 printf("DWMMC: MMC clock is zero!");
Marek Vasut17497232015-07-25 10:48:14 +020090 return -EINVAL;
Chin Liang Seecca9f452013-12-30 18:26:14 -060091 }
92
Marek Vasut26608602018-08-01 18:28:35 +020093 return 0;
94}
95
96static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
97{
98 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
99 struct dwmci_host *host = &priv->host;
100 int fifo_depth;
101
Simon Glassdd79d6e2017-01-17 16:52:55 -0700102 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100103 "fifo-depth", 0);
Marek Vasut17497232015-07-25 10:48:14 +0200104 if (fifo_depth < 0) {
Marek Vasutae66f3c2015-11-30 20:41:04 +0100105 printf("DWMMC: Can't get FIFO depth\n");
Marek Vasut17497232015-07-25 10:48:14 +0200106 return -EINVAL;
107 }
108
Marek Vasutae66f3c2015-11-30 20:41:04 +0100109 host->name = dev->name;
Simon Glassba1dea42017-05-17 17:18:05 -0600110 host->ioaddr = (void *)devfdt_get_addr(dev);
Simon Glassdd79d6e2017-01-17 16:52:55 -0700111 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100112 "bus-width", 4);
Chin Liang Seecca9f452013-12-30 18:26:14 -0600113 host->clksel = socfpga_dwmci_clksel;
Marek Vasutae66f3c2015-11-30 20:41:04 +0100114
115 /*
116 * TODO(sjg@chromium.org): Remove the need for this hack.
117 * We only have one dwmmc block on gen5 SoCFPGA.
118 */
119 host->dev_index = 0;
Chin Liang Seecca9f452013-12-30 18:26:14 -0600120 host->fifoth_val = MSIZE(0x2) |
Marek Vasut17497232015-07-25 10:48:14 +0200121 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
Simon Glassdd79d6e2017-01-17 16:52:55 -0700122 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100123 "drvsel", 3);
Simon Glassdd79d6e2017-01-17 16:52:55 -0700124 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100125 "smplsel", 0);
Chin Liang See48e7bf92015-11-26 09:43:43 +0800126 host->priv = priv;
Chin Liang Seecca9f452013-12-30 18:26:14 -0600127
Marek Vasutae66f3c2015-11-30 20:41:04 +0100128 return 0;
Chin Liang Seecca9f452013-12-30 18:26:14 -0600129}
130
Marek Vasutae66f3c2015-11-30 20:41:04 +0100131static int socfpga_dwmmc_probe(struct udevice *dev)
Marek Vasut17497232015-07-25 10:48:14 +0200132{
Simon Glassa3a43202016-07-05 17:10:16 -0600133#ifdef CONFIG_BLK
134 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
135#endif
Marek Vasutae66f3c2015-11-30 20:41:04 +0100136 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
137 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
138 struct dwmci_host *host = &priv->host;
Marek Vasut26608602018-08-01 18:28:35 +0200139 int ret;
140
141 ret = socfpga_dwmmc_get_clk_rate(dev);
142 if (ret)
143 return ret;
Simon Glassa3a43202016-07-05 17:10:16 -0600144
Ley Foon Tan5a694d02018-06-14 18:45:21 +0800145 socfpga_dwmci_reset(dev);
146
Simon Glassa3a43202016-07-05 17:10:16 -0600147#ifdef CONFIG_BLK
Jaehoon Chungbf819d02016-09-23 19:13:16 +0900148 dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
Simon Glassa3a43202016-07-05 17:10:16 -0600149 host->mmc = &plat->mmc;
150#else
Marek Vasut17497232015-07-25 10:48:14 +0200151
Marek Vasutae66f3c2015-11-30 20:41:04 +0100152 ret = add_dwmci(host, host->bus_hz, 400000);
153 if (ret)
154 return ret;
Simon Glassa3a43202016-07-05 17:10:16 -0600155#endif
156 host->mmc->priv = &priv->host;
Marek Vasutae66f3c2015-11-30 20:41:04 +0100157 upriv->mmc = host->mmc;
Simon Glass77ca42b2016-05-01 13:52:34 -0600158 host->mmc->dev = dev;
Marek Vasutae66f3c2015-11-30 20:41:04 +0100159
Patrick Bruenn3eab2202018-03-06 09:07:23 +0100160 return dwmci_probe(dev);
Marek Vasut17497232015-07-25 10:48:14 +0200161}
162
Simon Glassa3a43202016-07-05 17:10:16 -0600163static int socfpga_dwmmc_bind(struct udevice *dev)
164{
165#ifdef CONFIG_BLK
166 struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
167 int ret;
168
169 ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
170 if (ret)
171 return ret;
172#endif
173
174 return 0;
175}
176
Marek Vasutae66f3c2015-11-30 20:41:04 +0100177static const struct udevice_id socfpga_dwmmc_ids[] = {
178 { .compatible = "altr,socfpga-dw-mshc" },
179 { }
180};
Marek Vasut17497232015-07-25 10:48:14 +0200181
Marek Vasutae66f3c2015-11-30 20:41:04 +0100182U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
183 .name = "socfpga_dwmmc",
184 .id = UCLASS_MMC,
185 .of_match = socfpga_dwmmc_ids,
186 .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
Sylvain Lesne7083f912016-10-24 18:24:37 +0200187 .ops = &dm_dwmci_ops,
Simon Glassa3a43202016-07-05 17:10:16 -0600188 .bind = socfpga_dwmmc_bind,
Marek Vasutae66f3c2015-11-30 20:41:04 +0100189 .probe = socfpga_dwmmc_probe,
190 .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
Sylvain Lesne7083f912016-10-24 18:24:37 +0200191 .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
Marek Vasutae66f3c2015-11-30 20:41:04 +0100192};