Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Andreas Heppel <aheppel@sysgo.de> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef _PCI_H |
| 11 | #define _PCI_H |
| 12 | |
Minghuan Lian | c5bc6aa | 2015-07-10 11:35:08 +0800 | [diff] [blame] | 13 | #define PCI_CFG_SPACE_SIZE 256 |
| 14 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
| 15 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 16 | /* |
| 17 | * Under PCI, each device has 256 bytes of configuration address space, |
| 18 | * of which the first 64 bytes are standardized as follows: |
| 19 | */ |
Bin Meng | a7366f0 | 2018-08-03 01:14:52 -0700 | [diff] [blame] | 20 | #define PCI_STD_HEADER_SIZEOF 64 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 21 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
| 22 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
| 23 | #define PCI_COMMAND 0x04 /* 16 bits */ |
| 24 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
| 25 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
| 26 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ |
| 27 | #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ |
| 28 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
| 29 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ |
| 30 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ |
| 31 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
| 32 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
| 33 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
| 34 | |
| 35 | #define PCI_STATUS 0x06 /* 16 bits */ |
| 36 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ |
| 37 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
| 38 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
| 39 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
| 40 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
| 41 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
| 42 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
| 43 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
| 44 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
| 45 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
| 46 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
| 47 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
| 48 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
| 49 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
| 50 | |
| 51 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 |
| 52 | revision */ |
| 53 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
| 54 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
| 55 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
| 56 | #define PCI_CLASS_CODE 0x0b /* Device class code */ |
Bill Richardson | eece432 | 2012-10-20 11:44:34 +0000 | [diff] [blame] | 57 | #define PCI_CLASS_CODE_TOO_OLD 0x00 |
| 58 | #define PCI_CLASS_CODE_STORAGE 0x01 |
| 59 | #define PCI_CLASS_CODE_NETWORK 0x02 |
| 60 | #define PCI_CLASS_CODE_DISPLAY 0x03 |
| 61 | #define PCI_CLASS_CODE_MULTIMEDIA 0x04 |
| 62 | #define PCI_CLASS_CODE_MEMORY 0x05 |
| 63 | #define PCI_CLASS_CODE_BRIDGE 0x06 |
| 64 | #define PCI_CLASS_CODE_COMM 0x07 |
| 65 | #define PCI_CLASS_CODE_PERIPHERAL 0x08 |
| 66 | #define PCI_CLASS_CODE_INPUT 0x09 |
| 67 | #define PCI_CLASS_CODE_DOCKING 0x0A |
| 68 | #define PCI_CLASS_CODE_PROCESSOR 0x0B |
| 69 | #define PCI_CLASS_CODE_SERIAL 0x0C |
| 70 | #define PCI_CLASS_CODE_WIRELESS 0x0D |
| 71 | #define PCI_CLASS_CODE_I2O 0x0E |
| 72 | #define PCI_CLASS_CODE_SATELLITE 0x0F |
| 73 | #define PCI_CLASS_CODE_CRYPTO 0x10 |
| 74 | #define PCI_CLASS_CODE_DATA 0x11 |
| 75 | /* Base Class 0x12 - 0xFE is reserved */ |
| 76 | #define PCI_CLASS_CODE_OTHER 0xFF |
| 77 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 78 | #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ |
Bill Richardson | eece432 | 2012-10-20 11:44:34 +0000 | [diff] [blame] | 79 | #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 |
| 80 | #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 |
| 81 | #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 |
| 82 | #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 |
| 83 | #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 |
| 84 | #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 |
| 85 | #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 |
| 86 | #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 |
| 87 | #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 |
| 88 | #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 |
| 89 | #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 |
| 90 | #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 |
| 91 | #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 |
| 92 | #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 |
| 93 | #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 |
| 94 | #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 |
| 95 | #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 |
| 96 | #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 |
| 97 | #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 |
| 98 | #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 |
| 99 | #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 |
| 100 | #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 |
| 101 | #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 |
| 102 | #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 |
| 103 | #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 |
| 104 | #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 |
| 105 | #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 |
| 106 | #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 |
| 107 | #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 |
| 108 | #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 |
| 109 | #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 |
| 110 | #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 |
| 111 | #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 |
| 112 | #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 |
| 113 | #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 |
| 114 | #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 |
| 115 | #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 |
| 116 | #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 |
| 117 | #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 |
| 118 | #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 |
| 119 | #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A |
| 120 | #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 |
| 121 | #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 |
| 122 | #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 |
| 123 | #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 |
| 124 | #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 |
| 125 | #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 |
| 126 | #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 |
| 127 | #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 |
| 128 | #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 |
| 129 | #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 |
| 130 | #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 |
| 131 | #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 |
| 132 | #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 |
| 133 | #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 |
| 134 | #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 |
| 135 | #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 |
| 136 | #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 |
| 137 | #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 |
| 138 | #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 |
| 139 | #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 |
| 140 | #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 |
| 141 | #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 |
| 142 | #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 |
| 143 | #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 |
| 144 | #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 |
| 145 | #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 |
| 146 | #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 |
| 147 | #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 |
| 148 | #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 |
| 149 | #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 |
| 150 | #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 |
| 151 | #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 |
| 152 | #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 |
| 153 | #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 |
| 154 | #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 |
| 155 | #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 |
| 156 | #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 |
| 157 | #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 |
| 158 | #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 |
| 159 | #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 |
| 160 | #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 |
| 161 | #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 |
| 162 | #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 |
| 163 | #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 |
| 164 | #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 |
| 165 | #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 |
| 166 | #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 |
| 167 | #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 |
| 168 | #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 |
| 169 | #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 |
| 170 | #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 |
| 171 | #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 |
| 172 | #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 |
| 173 | #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 |
| 174 | #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 |
| 175 | #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 |
| 176 | #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 |
| 177 | #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 |
| 178 | #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 |
| 179 | #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 |
| 180 | #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 181 | |
| 182 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
| 183 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
| 184 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
| 185 | #define PCI_HEADER_TYPE_NORMAL 0 |
| 186 | #define PCI_HEADER_TYPE_BRIDGE 1 |
| 187 | #define PCI_HEADER_TYPE_CARDBUS 2 |
| 188 | |
| 189 | #define PCI_BIST 0x0f /* 8 bits */ |
| 190 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
| 191 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
| 192 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
| 193 | |
| 194 | /* |
| 195 | * Base addresses specify locations in memory or I/O space. |
| 196 | * Decoded size can be determined by writing a value of |
| 197 | * 0xffffffff to the register, and reading it back. Only |
| 198 | * 1 bits are decoded. |
| 199 | */ |
| 200 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
| 201 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ |
| 202 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ |
| 203 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
| 204 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
| 205 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
| 206 | #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
| 207 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
| 208 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
| 209 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 |
| 210 | #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ |
| 211 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ |
| 212 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
| 213 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
Kumar Gala | ad714f5 | 2008-10-21 08:36:08 -0500 | [diff] [blame] | 214 | #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) |
| 215 | #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 216 | /* bit 1 is reserved if address_space = 1 */ |
| 217 | |
Simon Glass | 130d7ff | 2019-09-25 08:56:06 -0600 | [diff] [blame] | 218 | /* Convert a regsister address (e.g. PCI_BASE_ADDRESS_1) to a bar # (e.g. 1) */ |
| 219 | #define pci_offset_to_barnum(offset) \ |
| 220 | (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32)) |
| 221 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 222 | /* Header type 0 (normal devices) */ |
| 223 | #define PCI_CARDBUS_CIS 0x28 |
| 224 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
| 225 | #define PCI_SUBSYSTEM_ID 0x2e |
| 226 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
| 227 | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
Kumar Gala | ad714f5 | 2008-10-21 08:36:08 -0500 | [diff] [blame] | 228 | #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 229 | |
| 230 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
| 231 | |
| 232 | /* 0x35-0x3b are reserved */ |
| 233 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
| 234 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
| 235 | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
| 236 | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
| 237 | |
Simon Glass | 84f5733 | 2015-07-27 15:47:17 -0600 | [diff] [blame] | 238 | #define PCI_INTERRUPT_LINE_DISABLE 0xff |
| 239 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 240 | /* Header type 1 (PCI-to-PCI bridges) */ |
| 241 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ |
| 242 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ |
| 243 | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ |
| 244 | #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ |
| 245 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ |
| 246 | #define PCI_IO_LIMIT 0x1d |
| 247 | #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ |
| 248 | #define PCI_IO_RANGE_TYPE_16 0x00 |
| 249 | #define PCI_IO_RANGE_TYPE_32 0x01 |
| 250 | #define PCI_IO_RANGE_MASK ~0x0f |
| 251 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
| 252 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
| 253 | #define PCI_MEMORY_LIMIT 0x22 |
| 254 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f |
| 255 | #define PCI_MEMORY_RANGE_MASK ~0x0f |
| 256 | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ |
| 257 | #define PCI_PREF_MEMORY_LIMIT 0x26 |
| 258 | #define PCI_PREF_RANGE_TYPE_MASK 0x0f |
| 259 | #define PCI_PREF_RANGE_TYPE_32 0x00 |
| 260 | #define PCI_PREF_RANGE_TYPE_64 0x01 |
| 261 | #define PCI_PREF_RANGE_MASK ~0x0f |
| 262 | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ |
| 263 | #define PCI_PREF_LIMIT_UPPER32 0x2c |
| 264 | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ |
| 265 | #define PCI_IO_LIMIT_UPPER16 0x32 |
| 266 | /* 0x34 same as for htype 0 */ |
| 267 | /* 0x35-0x3b is reserved */ |
| 268 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
| 269 | /* 0x3c-0x3d are same as for htype 0 */ |
| 270 | #define PCI_BRIDGE_CONTROL 0x3e |
| 271 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
| 272 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
| 273 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ |
| 274 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
| 275 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
| 276 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
| 277 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ |
| 278 | |
| 279 | /* Header type 2 (CardBus bridges) */ |
| 280 | #define PCI_CB_CAPABILITY_LIST 0x14 |
| 281 | /* 0x15 reserved */ |
| 282 | #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ |
| 283 | #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ |
| 284 | #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ |
| 285 | #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ |
| 286 | #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ |
| 287 | #define PCI_CB_MEMORY_BASE_0 0x1c |
| 288 | #define PCI_CB_MEMORY_LIMIT_0 0x20 |
| 289 | #define PCI_CB_MEMORY_BASE_1 0x24 |
| 290 | #define PCI_CB_MEMORY_LIMIT_1 0x28 |
| 291 | #define PCI_CB_IO_BASE_0 0x2c |
| 292 | #define PCI_CB_IO_BASE_0_HI 0x2e |
| 293 | #define PCI_CB_IO_LIMIT_0 0x30 |
| 294 | #define PCI_CB_IO_LIMIT_0_HI 0x32 |
| 295 | #define PCI_CB_IO_BASE_1 0x34 |
| 296 | #define PCI_CB_IO_BASE_1_HI 0x36 |
| 297 | #define PCI_CB_IO_LIMIT_1 0x38 |
| 298 | #define PCI_CB_IO_LIMIT_1_HI 0x3a |
| 299 | #define PCI_CB_IO_RANGE_MASK ~0x03 |
| 300 | /* 0x3c-0x3d are same as for htype 0 */ |
| 301 | #define PCI_CB_BRIDGE_CONTROL 0x3e |
| 302 | #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ |
| 303 | #define PCI_CB_BRIDGE_CTL_SERR 0x02 |
| 304 | #define PCI_CB_BRIDGE_CTL_ISA 0x04 |
| 305 | #define PCI_CB_BRIDGE_CTL_VGA 0x08 |
| 306 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 |
| 307 | #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ |
| 308 | #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ |
| 309 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ |
| 310 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 |
| 311 | #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 |
| 312 | #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 |
| 313 | #define PCI_CB_SUBSYSTEM_ID 0x42 |
| 314 | #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ |
| 315 | /* 0x48-0x7f reserved */ |
| 316 | |
| 317 | /* Capability lists */ |
| 318 | |
| 319 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
| 320 | #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
| 321 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
| 322 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
| 323 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
| 324 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
| 325 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
Bin Meng | 16541e8 | 2018-08-03 01:14:51 -0700 | [diff] [blame] | 326 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
| 327 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
| 328 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ |
| 329 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ |
| 330 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ |
| 331 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
| 332 | #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ |
| 333 | #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ |
| 334 | #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ |
| 335 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
| 336 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
| 337 | #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ |
| 338 | #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ |
| 339 | #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ |
| 340 | #define PCI_CAP_ID_MAX PCI_CAP_ID_EA |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 341 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
| 342 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
| 343 | #define PCI_CAP_SIZEOF 4 |
| 344 | |
| 345 | /* Power Management Registers */ |
| 346 | |
| 347 | #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ |
| 348 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ |
| 349 | #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ |
| 350 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ |
| 351 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
| 352 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ |
| 353 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ |
| 354 | #define PCI_PM_CTRL 4 /* PM control and status register */ |
| 355 | #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ |
| 356 | #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ |
| 357 | #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ |
| 358 | #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ |
| 359 | #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ |
| 360 | #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ |
| 361 | #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ |
| 362 | #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ |
| 363 | #define PCI_PM_DATA_REGISTER 7 /* (??) */ |
| 364 | #define PCI_PM_SIZEOF 8 |
| 365 | |
| 366 | /* AGP registers */ |
| 367 | |
| 368 | #define PCI_AGP_VERSION 2 /* BCD version number */ |
| 369 | #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
| 370 | #define PCI_AGP_STATUS 4 /* Status register */ |
| 371 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
| 372 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
| 373 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
| 374 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
| 375 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
| 376 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
| 377 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
| 378 | #define PCI_AGP_COMMAND 8 /* Control register */ |
| 379 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
| 380 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
| 381 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
| 382 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
| 383 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
| 384 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
| 385 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ |
| 386 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ |
| 387 | #define PCI_AGP_SIZEOF 12 |
| 388 | |
Matthew McClintock | 3fc12c5 | 2006-06-28 10:44:49 -0500 | [diff] [blame] | 389 | /* PCI-X registers */ |
| 390 | |
| 391 | #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
| 392 | #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ |
| 393 | #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ |
| 394 | #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ |
| 395 | #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ |
| 396 | |
| 397 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 398 | /* Slot Identification */ |
| 399 | |
| 400 | #define PCI_SID_ESR 2 /* Expansion Slot Register */ |
| 401 | #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ |
| 402 | #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ |
| 403 | #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ |
| 404 | |
| 405 | /* Message Signalled Interrupts registers */ |
| 406 | |
| 407 | #define PCI_MSI_FLAGS 2 /* Various flags */ |
| 408 | #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ |
| 409 | #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ |
| 410 | #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ |
| 411 | #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ |
Ramon Fried | 8a8e86f | 2019-04-06 05:12:01 +0300 | [diff] [blame] | 412 | #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 413 | #define PCI_MSI_RFU 3 /* Rest of capability flags */ |
| 414 | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ |
| 415 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
| 416 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
| 417 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
| 418 | |
| 419 | #define PCI_MAX_PCI_DEVICES 32 |
| 420 | #define PCI_MAX_PCI_FUNCTIONS 8 |
| 421 | |
Zhao Qiang | 5d39f74 | 2013-10-12 13:46:33 +0800 | [diff] [blame] | 422 | #define PCI_FIND_CAP_TTL 0x48 |
| 423 | #define CAP_START_POS 0x40 |
| 424 | |
Minghuan Lian | c5bc6aa | 2015-07-10 11:35:08 +0800 | [diff] [blame] | 425 | /* Extended Capabilities (PCI-X 2.0 and Express) */ |
| 426 | #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) |
| 427 | #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) |
| 428 | #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) |
| 429 | |
| 430 | #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ |
| 431 | #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ |
| 432 | #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ |
| 433 | #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ |
| 434 | #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ |
| 435 | #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ |
| 436 | #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ |
| 437 | #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ |
| 438 | #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ |
| 439 | #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ |
| 440 | #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ |
| 441 | #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ |
| 442 | #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ |
| 443 | #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ |
| 444 | #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ |
| 445 | #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ |
| 446 | #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ |
| 447 | #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ |
| 448 | #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ |
| 449 | #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ |
| 450 | #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ |
| 451 | #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ |
| 452 | #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ |
| 453 | #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ |
| 454 | #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ |
| 455 | #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ |
| 456 | #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ |
Bin Meng | 16541e8 | 2018-08-03 01:14:51 -0700 | [diff] [blame] | 457 | #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ |
| 458 | #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ |
| 459 | #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ |
| 460 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM |
Minghuan Lian | c5bc6aa | 2015-07-10 11:35:08 +0800 | [diff] [blame] | 461 | |
Alex Marginean | 1c934a6 | 2019-06-07 11:24:23 +0300 | [diff] [blame] | 462 | /* Enhanced Allocation Registers */ |
| 463 | #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */ |
| 464 | #define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ |
| 465 | #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ |
| 466 | #define PCI_EA_ES 0x00000007 /* Entry Size */ |
| 467 | #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ |
Suneel Garapati | 5858ba8 | 2019-10-19 16:34:16 -0700 | [diff] [blame] | 468 | /* 9-14 map to VF BARs 0-5 respectively */ |
| 469 | #define PCI_EA_BEI_VF_BAR0 9 |
| 470 | #define PCI_EA_BEI_VF_BAR5 14 |
Alex Marginean | 1c934a6 | 2019-06-07 11:24:23 +0300 | [diff] [blame] | 471 | /* Base, MaxOffset registers */ |
| 472 | /* bit 0 is reserved */ |
| 473 | #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ |
| 474 | #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ |
| 475 | |
Alex Marginean | 09467d3 | 2019-06-07 11:24:25 +0300 | [diff] [blame] | 476 | /* PCI Express capabilities */ |
Sylwester Nawrocki | 2d0ee24 | 2020-05-25 13:39:53 +0200 | [diff] [blame] | 477 | #define PCI_EXP_FLAGS 2 /* Capabilities register */ |
| 478 | #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ |
| 479 | #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ |
Alex Marginean | 09467d3 | 2019-06-07 11:24:25 +0300 | [diff] [blame] | 480 | #define PCI_EXP_DEVCAP 4 /* Device capabilities */ |
Sylwester Nawrocki | 2d0ee24 | 2020-05-25 13:39:53 +0200 | [diff] [blame] | 481 | #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ |
Alex Marginean | 09467d3 | 2019-06-07 11:24:25 +0300 | [diff] [blame] | 482 | #define PCI_EXP_DEVCTL 8 /* Device Control */ |
Sylwester Nawrocki | 2d0ee24 | 2020-05-25 13:39:53 +0200 | [diff] [blame] | 483 | #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ |
| 484 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
Sylwester Nawrocki | df1cb96 | 2020-05-25 13:39:57 +0200 | [diff] [blame] | 485 | #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ |
| 486 | #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ |
Sylwester Nawrocki | 2d0ee24 | 2020-05-25 13:39:53 +0200 | [diff] [blame] | 487 | #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ |
| 488 | #define PCI_EXP_LNKSTA 18 /* Link Status */ |
Sylwester Nawrocki | df1cb96 | 2020-05-25 13:39:57 +0200 | [diff] [blame] | 489 | #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ |
| 490 | #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ |
| 491 | #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ |
| 492 | #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ |
| 493 | #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ |
| 494 | #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ |
Sylwester Nawrocki | 2d0ee24 | 2020-05-25 13:39:53 +0200 | [diff] [blame] | 495 | #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ |
| 496 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
| 497 | #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ |
Pali Rohár | 238fbab | 2021-09-26 00:54:44 +0200 | [diff] [blame] | 498 | #define PCI_EXP_RTCTL 28 /* Root Control */ |
| 499 | #define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ |
| 500 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
| 501 | #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ |
Laurentiu Tudor | 1333e90 | 2020-09-10 12:42:18 +0300 | [diff] [blame] | 502 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
| 503 | #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */ |
| 504 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ |
| 505 | #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ |
| 506 | |
Sylwester Nawrocki | df1cb96 | 2020-05-25 13:39:57 +0200 | [diff] [blame] | 507 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
Suneel Garapati | 13822f7 | 2019-10-19 16:07:20 -0700 | [diff] [blame] | 508 | /* Single Root I/O Virtualization Registers */ |
| 509 | #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ |
| 510 | #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ |
| 511 | #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ |
| 512 | #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ |
Laurentiu Tudor | 1333e90 | 2020-09-10 12:42:18 +0300 | [diff] [blame] | 513 | #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ |
Suneel Garapati | 13822f7 | 2019-10-19 16:07:20 -0700 | [diff] [blame] | 514 | #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ |
| 515 | #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ |
| 516 | #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ |
| 517 | #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ |
| 518 | #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ |
| 519 | #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ |
Alex Marginean | 09467d3 | 2019-06-07 11:24:25 +0300 | [diff] [blame] | 520 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 521 | /* Include the ID list */ |
| 522 | |
| 523 | #include <pci_ids.h> |
| 524 | |
Pali Rohár | 2376935 | 2021-11-03 01:01:05 +0100 | [diff] [blame] | 525 | /* |
| 526 | * Enhanced Configuration Access Mechanism (ECAM) |
| 527 | * |
| 528 | * See PCI Express Base Specification, Revision 5.0, Version 1.0, |
| 529 | * Section 7.2.2, Table 7-1, p. 677. |
| 530 | */ |
| 531 | #define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */ |
| 532 | #define PCIE_ECAM_DEV_SHIFT 15 /* Device number */ |
| 533 | #define PCIE_ECAM_FUNC_SHIFT 12 /* Function number */ |
| 534 | |
| 535 | #define PCIE_ECAM_BUS_MASK 0xff |
| 536 | #define PCIE_ECAM_DEV_MASK 0x1f |
| 537 | #define PCIE_ECAM_FUNC_MASK 0x7 |
| 538 | #define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */ |
| 539 | |
| 540 | #define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT) |
| 541 | #define PCIE_ECAM_DEV(x) (((x) & PCIE_ECAM_DEV_MASK) << PCIE_ECAM_DEV_SHIFT) |
| 542 | #define PCIE_ECAM_FUNC(x) (((x) & PCIE_ECAM_FUNC_MASK) << PCIE_ECAM_FUNC_SHIFT) |
| 543 | #define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK) |
| 544 | |
| 545 | #define PCIE_ECAM_OFFSET(bus, dev, func, where) \ |
| 546 | (PCIE_ECAM_BUS(bus) | \ |
| 547 | PCIE_ECAM_DEV(dev) | \ |
| 548 | PCIE_ECAM_FUNC(func) | \ |
| 549 | PCIE_ECAM_REG(where)) |
| 550 | |
Paul Burton | 162116e | 2013-11-08 11:18:47 +0000 | [diff] [blame] | 551 | #ifndef __ASSEMBLY__ |
| 552 | |
Simon Glass | 0b591e0 | 2019-12-06 21:41:38 -0700 | [diff] [blame] | 553 | #include <dm/pci.h> |
| 554 | |
Kumar Gala | ad714f5 | 2008-10-21 08:36:08 -0500 | [diff] [blame] | 555 | #ifdef CONFIG_SYS_PCI_64BIT |
| 556 | typedef u64 pci_addr_t; |
| 557 | typedef u64 pci_size_t; |
| 558 | #else |
Heinrich Schuchardt | 149ccf3 | 2020-02-05 21:59:12 +0100 | [diff] [blame] | 559 | typedef unsigned long pci_addr_t; |
| 560 | typedef unsigned long pci_size_t; |
Kumar Gala | ad714f5 | 2008-10-21 08:36:08 -0500 | [diff] [blame] | 561 | #endif |
| 562 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 563 | struct pci_region { |
Kumar Gala | ad714f5 | 2008-10-21 08:36:08 -0500 | [diff] [blame] | 564 | pci_addr_t bus_start; /* Start on the bus */ |
| 565 | phys_addr_t phys_start; /* Start in physical address space */ |
| 566 | pci_size_t size; /* Size */ |
| 567 | unsigned long flags; /* Resource flags */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 568 | |
Kumar Gala | ad714f5 | 2008-10-21 08:36:08 -0500 | [diff] [blame] | 569 | pci_addr_t bus_lower; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 570 | }; |
| 571 | |
| 572 | #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ |
| 573 | #define PCI_REGION_IO 0x00000001 /* PCI IO space */ |
| 574 | #define PCI_REGION_TYPE 0x00000001 |
Kumar Gala | e5ce420 | 2006-01-11 13:24:15 -0600 | [diff] [blame] | 575 | #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 576 | |
Kumar Gala | efa1f1d | 2009-02-06 09:49:31 -0600 | [diff] [blame] | 577 | #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 578 | #define PCI_REGION_RO 0x00000200 /* Read-only memory */ |
| 579 | |
Simon Glass | 64f11d0 | 2013-06-11 11:14:33 -0700 | [diff] [blame] | 580 | static inline void pci_set_region(struct pci_region *reg, |
Kumar Gala | ad714f5 | 2008-10-21 08:36:08 -0500 | [diff] [blame] | 581 | pci_addr_t bus_start, |
Becky Bruce | 0a62857 | 2008-05-07 13:24:57 -0500 | [diff] [blame] | 582 | phys_addr_t phys_start, |
Kumar Gala | ad714f5 | 2008-10-21 08:36:08 -0500 | [diff] [blame] | 583 | pci_size_t size, |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 584 | unsigned long flags) { |
| 585 | reg->bus_start = bus_start; |
| 586 | reg->phys_start = phys_start; |
| 587 | reg->size = size; |
| 588 | reg->flags = flags; |
| 589 | } |
| 590 | |
| 591 | typedef int pci_dev_t; |
| 592 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 593 | #define PCI_BUS(d) (((d) >> 16) & 0xff) |
Stefan Roese | 97a8bbf | 2019-02-11 08:43:25 +0100 | [diff] [blame] | 594 | |
| 595 | /* |
| 596 | * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot |
| 597 | * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0. |
| 598 | * Please see the Linux header include/uapi/linux/pci.h for more details. |
| 599 | * This is relevant for the following macros: |
| 600 | * PCI_DEV, PCI_FUNC, PCI_DEVFN |
| 601 | * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with |
Simon Glass | 951be47 | 2020-05-10 10:26:54 -0600 | [diff] [blame] | 602 | * the remark from above (input is in bits 15-8 instead of 7-0. |
Stefan Roese | 97a8bbf | 2019-02-11 08:43:25 +0100 | [diff] [blame] | 603 | */ |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 604 | #define PCI_DEV(d) (((d) >> 11) & 0x1f) |
| 605 | #define PCI_FUNC(d) (((d) >> 8) & 0x7) |
| 606 | #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) |
Stefan Roese | 97a8bbf | 2019-02-11 08:43:25 +0100 | [diff] [blame] | 607 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 608 | #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) |
| 609 | #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) |
| 610 | #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 611 | #define PCI_ANY_ID (~0) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 612 | |
Simon Glass | baefa09 | 2020-04-08 08:32:59 -0600 | [diff] [blame] | 613 | /* Convert from Linux format to U-Boot format */ |
| 614 | #define PCI_TO_BDF(val) ((val) << 8) |
| 615 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 616 | struct pci_device_id { |
Simon Glass | 318d71c | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 617 | unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ |
| 618 | unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ |
| 619 | unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ |
| 620 | unsigned long driver_data; /* Data private to the driver */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 621 | }; |
| 622 | |
| 623 | struct pci_controller; |
| 624 | |
| 625 | struct pci_config_table { |
| 626 | unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ |
| 627 | unsigned int class; /* Class ID, or PCI_ANY_ID */ |
| 628 | unsigned int bus; /* Bus number, or PCI_ANY_ID */ |
| 629 | unsigned int dev; /* Device number, or PCI_ANY_ID */ |
| 630 | unsigned int func; /* Function number, or PCI_ANY_ID */ |
| 631 | |
| 632 | void (*config_device)(struct pci_controller* hose, pci_dev_t dev, |
| 633 | struct pci_config_table *); |
| 634 | unsigned long priv[3]; |
| 635 | }; |
| 636 | |
Wolfgang Denk | 3d7f5e0 | 2006-03-12 16:54:11 +0100 | [diff] [blame] | 637 | extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, |
| 638 | struct pci_config_table *); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 639 | extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, |
| 640 | struct pci_config_table *); |
| 641 | |
Anton Vorontsov | 1a8206c | 2009-01-08 04:26:12 +0300 | [diff] [blame] | 642 | #define INDIRECT_TYPE_NO_PCIE_LINK 1 |
| 643 | |
Simon Glass | 68e35a7 | 2019-12-06 21:41:37 -0700 | [diff] [blame] | 644 | /** |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 645 | * Structure of a PCI controller (host bridge) |
Simon Glass | c19e442 | 2015-11-26 19:51:21 -0700 | [diff] [blame] | 646 | * |
| 647 | * With driver model this is dev_get_uclass_priv(bus) |
Simon Glass | 68e35a7 | 2019-12-06 21:41:37 -0700 | [diff] [blame] | 648 | * |
| 649 | * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has |
| 650 | * relocated. Normally if PCI is used before relocation, this happens |
| 651 | * before relocation also. Some platforms set up static configuration in |
| 652 | * TPL/SPL to reduce code size and boot time, since these phases only know |
| 653 | * about a small subset of PCI devices. This is normally false. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 654 | */ |
| 655 | struct pci_controller { |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 656 | struct udevice *bus; |
| 657 | struct udevice *ctlr; |
Simon Glass | 68e35a7 | 2019-12-06 21:41:37 -0700 | [diff] [blame] | 658 | bool skip_auto_config_until_reloc; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 659 | |
| 660 | int first_busno; |
| 661 | int last_busno; |
| 662 | |
| 663 | volatile unsigned int *cfg_addr; |
| 664 | volatile unsigned char *cfg_data; |
| 665 | |
Anton Vorontsov | 1a8206c | 2009-01-08 04:26:12 +0300 | [diff] [blame] | 666 | int indirect_type; |
| 667 | |
Simon Glass | d82fbe9 | 2015-06-07 08:50:40 -0600 | [diff] [blame] | 668 | /* |
| 669 | * TODO(sjg@chromium.org): With driver model we use struct |
| 670 | * pci_controller for both the controller and any bridge devices |
| 671 | * attached to it. But there is only one region list and it is in the |
| 672 | * top-level controller. |
| 673 | * |
| 674 | * This could be changed so that struct pci_controller is only used |
| 675 | * for PCI controllers and a separate UCLASS (or perhaps |
| 676 | * UCLASS_PCI_GENERIC) is used for bridges. |
| 677 | */ |
Stefan Roese | 950864f | 2020-07-23 16:34:10 +0200 | [diff] [blame] | 678 | struct pci_region *regions; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 679 | int region_count; |
| 680 | |
| 681 | struct pci_config_table *config_table; |
| 682 | |
| 683 | void (*fixup_irq)(struct pci_controller *, pci_dev_t); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 684 | |
| 685 | /* Used by auto config */ |
Kumar Gala | e5ce420 | 2006-01-11 13:24:15 -0600 | [diff] [blame] | 686 | struct pci_region *pci_mem, *pci_io, *pci_prefetch; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 687 | }; |
| 688 | |
Simon Glass | 3dba83b | 2021-08-01 18:54:16 -0600 | [diff] [blame] | 689 | #if defined(CONFIG_DM_PCI_COMPAT) |
Becky Bruce | 0a62857 | 2008-05-07 13:24:57 -0500 | [diff] [blame] | 690 | extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, |
Kumar Gala | ad714f5 | 2008-10-21 08:36:08 -0500 | [diff] [blame] | 691 | pci_addr_t addr, unsigned long flags); |
| 692 | extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, |
| 693 | phys_addr_t addr, unsigned long flags); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 694 | |
| 695 | #define pci_phys_to_bus(dev, addr, flags) \ |
| 696 | pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) |
| 697 | #define pci_bus_to_phys(dev, addr, flags) \ |
| 698 | pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) |
| 699 | |
Becky Bruce | 0709bfc | 2009-02-03 18:10:50 -0600 | [diff] [blame] | 700 | #define pci_virt_to_bus(dev, addr, flags) \ |
| 701 | pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ |
| 702 | (virt_to_phys(addr)), (flags)) |
| 703 | #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ |
| 704 | map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ |
| 705 | (addr), (flags)), \ |
| 706 | (len), (map_flags)) |
| 707 | |
| 708 | #define pci_phys_to_mem(dev, addr) \ |
| 709 | pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) |
| 710 | #define pci_mem_to_phys(dev, addr) \ |
| 711 | pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) |
| 712 | #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) |
| 713 | #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) |
| 714 | |
| 715 | #define pci_virt_to_mem(dev, addr) \ |
| 716 | pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) |
| 717 | #define pci_mem_to_virt(dev, addr, len, map_flags) \ |
| 718 | pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) |
| 719 | #define pci_virt_to_io(dev, addr) \ |
| 720 | pci_virt_to_bus((dev), (addr), PCI_REGION_IO) |
| 721 | #define pci_io_to_virt(dev, addr, len, map_flags) \ |
| 722 | pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 723 | |
Simon Glass | f2b223f | 2015-08-22 15:58:55 -0600 | [diff] [blame] | 724 | /* For driver model these are defined in macros in pci_compat.c */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 725 | extern int pci_hose_read_config_byte(struct pci_controller *hose, |
| 726 | pci_dev_t dev, int where, u8 *val); |
| 727 | extern int pci_hose_read_config_word(struct pci_controller *hose, |
| 728 | pci_dev_t dev, int where, u16 *val); |
| 729 | extern int pci_hose_read_config_dword(struct pci_controller *hose, |
| 730 | pci_dev_t dev, int where, u32 *val); |
| 731 | extern int pci_hose_write_config_byte(struct pci_controller *hose, |
| 732 | pci_dev_t dev, int where, u8 val); |
| 733 | extern int pci_hose_write_config_word(struct pci_controller *hose, |
| 734 | pci_dev_t dev, int where, u16 val); |
| 735 | extern int pci_hose_write_config_dword(struct pci_controller *hose, |
| 736 | pci_dev_t dev, int where, u32 val); |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 737 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 738 | |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 739 | void pciauto_region_init(struct pci_region *res); |
| 740 | void pciauto_region_align(struct pci_region *res, pci_size_t size); |
| 741 | void pciauto_config_init(struct pci_controller *hose); |
Tuomas Tynkkynen | ffa21e9 | 2018-05-14 23:50:05 +0300 | [diff] [blame] | 742 | |
| 743 | /** |
| 744 | * pciauto_region_allocate() - Allocate resources from a PCI resource region |
| 745 | * |
| 746 | * Allocates @size bytes from the PCI resource @res. If @supports_64bit is |
| 747 | * false, the result will be guaranteed to fit in 32 bits. |
| 748 | * |
| 749 | * @res: PCI region to allocate from |
| 750 | * @size: Amount of bytes to allocate |
| 751 | * @bar: Returns the PCI bus address of the allocated resource |
| 752 | * @supports_64bit: Whether to allow allocations above the 32-bit boundary |
| 753 | * @return 0 if successful, -1 on failure |
| 754 | */ |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 755 | int pciauto_region_allocate(struct pci_region *res, pci_size_t size, |
Tuomas Tynkkynen | f20b718 | 2018-05-14 19:38:13 +0300 | [diff] [blame] | 756 | pci_addr_t *bar, bool supports_64bit); |
Vladimir Oltean | 6942c88 | 2021-09-17 15:11:20 +0300 | [diff] [blame] | 757 | int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 758 | |
Simon Glass | 3dba83b | 2021-08-01 18:54:16 -0600 | [diff] [blame] | 759 | #if defined(CONFIG_DM_PCI_COMPAT) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 760 | extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, |
| 761 | pci_dev_t dev, int where, u8 *val); |
| 762 | extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, |
| 763 | pci_dev_t dev, int where, u16 *val); |
| 764 | extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, |
| 765 | pci_dev_t dev, int where, u8 val); |
| 766 | extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, |
| 767 | pci_dev_t dev, int where, u16 val); |
| 768 | |
Becky Bruce | 0709bfc | 2009-02-03 18:10:50 -0600 | [diff] [blame] | 769 | extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 770 | extern void pci_register_hose(struct pci_controller* hose); |
| 771 | extern struct pci_controller* pci_bus_to_hose(int bus); |
Kumar Gala | db943ed | 2010-12-17 05:57:25 -0600 | [diff] [blame] | 772 | extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); |
Stuart Yoder | f950305 | 2016-03-10 10:52:18 -0600 | [diff] [blame] | 773 | extern struct pci_controller *pci_get_hose_head(void); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 774 | |
| 775 | extern int pci_hose_scan(struct pci_controller *hose); |
| 776 | extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); |
| 777 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 778 | extern void pciauto_setup_device(struct pci_controller *hose, |
| 779 | pci_dev_t dev, int bars_num, |
| 780 | struct pci_region *mem, |
Kumar Gala | e5ce420 | 2006-01-11 13:24:15 -0600 | [diff] [blame] | 781 | struct pci_region *prefetch, |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 782 | struct pci_region *io); |
Linus Walleij | 0053272 | 2012-03-25 12:13:15 +0000 | [diff] [blame] | 783 | extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, |
| 784 | pci_dev_t dev, int sub_bus); |
| 785 | extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, |
| 786 | pci_dev_t dev, int sub_bus); |
Linus Walleij | 0053272 | 2012-03-25 12:13:15 +0000 | [diff] [blame] | 787 | extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 788 | |
| 789 | extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); |
| 790 | extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); |
Simon Glass | 62034ff | 2015-01-27 22:13:27 -0700 | [diff] [blame] | 791 | pci_dev_t pci_find_class(unsigned int find_class, int index); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 792 | |
Zhao Qiang | 5d39f74 | 2013-10-12 13:46:33 +0800 | [diff] [blame] | 793 | extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, |
| 794 | int cap); |
| 795 | extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, |
| 796 | u8 hdr_type); |
| 797 | extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, |
| 798 | int cap); |
| 799 | |
Minghuan Lian | c5bc6aa | 2015-07-10 11:35:08 +0800 | [diff] [blame] | 800 | int pci_find_next_ext_capability(struct pci_controller *hose, |
| 801 | pci_dev_t dev, int start, int cap); |
| 802 | int pci_hose_find_ext_capability(struct pci_controller *hose, |
| 803 | pci_dev_t dev, int cap); |
| 804 | |
Simon Glass | 3dba83b | 2021-08-01 18:54:16 -0600 | [diff] [blame] | 805 | #endif /* defined(CONFIG_DM_PCI_COMPAT) */ |
Tim Harvey | 231c076 | 2014-08-07 22:49:56 -0700 | [diff] [blame] | 806 | |
Peter Tyser | 22ccb7f | 2010-10-29 17:59:27 -0500 | [diff] [blame] | 807 | const char * pci_class_str(u8 class); |
Anton Vorontsov | 597b8c4 | 2009-02-19 18:20:41 +0300 | [diff] [blame] | 808 | int pci_last_busno(void); |
| 809 | |
Jon Loeliger | c934adb | 2006-10-19 11:33:52 -0500 | [diff] [blame] | 810 | #ifdef CONFIG_MPC85xx |
| 811 | extern void pci_mpc85xx_init (struct pci_controller *hose); |
| 812 | #endif |
Paul Burton | 162116e | 2013-11-08 11:18:47 +0000 | [diff] [blame] | 813 | |
Simon Glass | 6ac5af4 | 2014-11-14 18:18:30 -0700 | [diff] [blame] | 814 | /** |
| 815 | * pci_write_bar32() - Write the address of a BAR including control bits |
| 816 | * |
Simon Glass | e2b6b56 | 2016-01-18 20:19:15 -0700 | [diff] [blame] | 817 | * This writes a raw address (with control bits) to a bar. This can be used |
| 818 | * with devices which require hard-coded addresses, not part of the normal |
| 819 | * PCI enumeration process. |
Simon Glass | 6ac5af4 | 2014-11-14 18:18:30 -0700 | [diff] [blame] | 820 | * |
Simon Glass | 55b6a27 | 2021-08-01 18:54:17 -0600 | [diff] [blame] | 821 | * This is only available if CONFIG_DM_PCI_COMPAT is enabled |
| 822 | * |
Simon Glass | 6ac5af4 | 2014-11-14 18:18:30 -0700 | [diff] [blame] | 823 | * @hose: PCI hose to use |
| 824 | * @dev: PCI device to update |
| 825 | * @barnum: BAR number (0-5) |
| 826 | * @addr: BAR address with control bits |
| 827 | */ |
| 828 | void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, |
Simon Glass | e2b6b56 | 2016-01-18 20:19:15 -0700 | [diff] [blame] | 829 | u32 addr); |
Simon Glass | 6ac5af4 | 2014-11-14 18:18:30 -0700 | [diff] [blame] | 830 | |
| 831 | /** |
| 832 | * pci_read_bar32() - read the address of a bar |
| 833 | * |
Simon Glass | 55b6a27 | 2021-08-01 18:54:17 -0600 | [diff] [blame] | 834 | * This is only available if CONFIG_DM_PCI_COMPAT is enabled |
| 835 | * |
Simon Glass | 6ac5af4 | 2014-11-14 18:18:30 -0700 | [diff] [blame] | 836 | * @hose: PCI hose to use |
| 837 | * @dev: PCI device to inspect |
| 838 | * @barnum: BAR number (0-5) |
| 839 | * @return address of the bar, masking out any control bits |
| 840 | * */ |
| 841 | u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); |
| 842 | |
Simon Glass | 1c1695b | 2015-01-14 21:37:04 -0700 | [diff] [blame] | 843 | /** |
Simon Glass | 75532d8 | 2015-03-05 12:25:24 -0700 | [diff] [blame] | 844 | * pci_hose_find_devices() - Find devices by vendor/device ID |
| 845 | * |
Simon Glass | 55b6a27 | 2021-08-01 18:54:17 -0600 | [diff] [blame] | 846 | * This is only available if CONFIG_DM_PCI_COMPAT is enabled |
| 847 | * |
Simon Glass | 75532d8 | 2015-03-05 12:25:24 -0700 | [diff] [blame] | 848 | * @hose: PCI hose to search |
| 849 | * @busnum: Bus number to search |
| 850 | * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record |
| 851 | * @indexp: Pointer to device index to find. To find the first matching |
| 852 | * device, pass 0; to find the second, pass 1, etc. This |
| 853 | * parameter is decremented for each non-matching device so |
| 854 | * can be called repeatedly. |
| 855 | */ |
| 856 | pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, |
| 857 | struct pci_device_id *ids, int *indexp); |
| 858 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 859 | /* Access sizes for PCI reads and writes */ |
| 860 | enum pci_size_t { |
| 861 | PCI_SIZE_8, |
| 862 | PCI_SIZE_16, |
| 863 | PCI_SIZE_32, |
| 864 | }; |
| 865 | |
| 866 | struct udevice; |
| 867 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 868 | /** |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 869 | * struct pci_child_plat - information stored about each PCI device |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 870 | * |
| 871 | * Every device on a PCI bus has this per-child data. |
| 872 | * |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 873 | * It can be accessed using dev_get_parent_plat(dev) if dev->parent is a |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 874 | * PCI bus (i.e. UCLASS_PCI) |
| 875 | * |
| 876 | * @devfn: Encoded device and function index - see PCI_DEVFN() |
| 877 | * @vendor: PCI vendor ID (see pci_ids.h) |
| 878 | * @device: PCI device ID (see pci_ids.h) |
| 879 | * @class: PCI class, 3 bytes: (base, sub, prog-if) |
Suneel Garapati | 13822f7 | 2019-10-19 16:07:20 -0700 | [diff] [blame] | 880 | * @is_virtfn: True for Virtual Function device |
| 881 | * @pfdev: Handle to Physical Function device |
| 882 | * @virtid: Virtual Function Index |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 883 | */ |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 884 | struct pci_child_plat { |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 885 | int devfn; |
| 886 | unsigned short vendor; |
| 887 | unsigned short device; |
| 888 | unsigned int class; |
Suneel Garapati | 13822f7 | 2019-10-19 16:07:20 -0700 | [diff] [blame] | 889 | |
| 890 | /* Variables for CONFIG_PCI_SRIOV */ |
| 891 | bool is_virtfn; |
| 892 | struct udevice *pfdev; |
| 893 | int virtid; |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 894 | }; |
| 895 | |
| 896 | /* PCI bus operations */ |
| 897 | struct dm_pci_ops { |
| 898 | /** |
| 899 | * read_config() - Read a PCI configuration value |
| 900 | * |
| 901 | * PCI buses must support reading and writing configuration values |
| 902 | * so that the bus can be scanned and its devices configured. |
| 903 | * |
Simon Glass | 75e534b | 2020-12-16 21:20:07 -0700 | [diff] [blame] | 904 | * Normally PCI_BUS(@bdf) is the same as @dev_seq(bus), but not always. |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 905 | * If bridges exist it is possible to use the top-level bus to |
| 906 | * access a sub-bus. In that case @bus will be the top-level bus |
| 907 | * and PCI_BUS(bdf) will be a different (higher) value |
| 908 | * |
| 909 | * @bus: Bus to read from |
| 910 | * @bdf: Bus, device and function to read |
| 911 | * @offset: Byte offset within the device's configuration space |
| 912 | * @valuep: Place to put the returned value |
| 913 | * @size: Access size |
| 914 | * @return 0 if OK, -ve on error |
| 915 | */ |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 916 | int (*read_config)(const struct udevice *bus, pci_dev_t bdf, |
| 917 | uint offset, ulong *valuep, enum pci_size_t size); |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 918 | /** |
| 919 | * write_config() - Write a PCI configuration value |
| 920 | * |
| 921 | * @bus: Bus to write to |
| 922 | * @bdf: Bus, device and function to write |
| 923 | * @offset: Byte offset within the device's configuration space |
| 924 | * @value: Value to write |
| 925 | * @size: Access size |
| 926 | * @return 0 if OK, -ve on error |
| 927 | */ |
| 928 | int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, |
| 929 | ulong value, enum pci_size_t size); |
| 930 | }; |
| 931 | |
| 932 | /* Get access to a PCI bus' operations */ |
| 933 | #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) |
| 934 | |
| 935 | /** |
Simon Glass | eaa1489 | 2015-11-29 13:17:47 -0700 | [diff] [blame] | 936 | * dm_pci_get_bdf() - Get the BDF value for a device |
Simon Glass | c9118d4 | 2015-07-06 16:47:46 -0600 | [diff] [blame] | 937 | * |
| 938 | * @dev: Device to check |
| 939 | * @return bus/device/function value (see PCI_BDF()) |
| 940 | */ |
Simon Glass | c92aac1 | 2020-01-27 08:49:38 -0700 | [diff] [blame] | 941 | pci_dev_t dm_pci_get_bdf(const struct udevice *dev); |
Simon Glass | c9118d4 | 2015-07-06 16:47:46 -0600 | [diff] [blame] | 942 | |
| 943 | /** |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 944 | * pci_bind_bus_devices() - scan a PCI bus and bind devices |
| 945 | * |
| 946 | * Scan a PCI bus looking for devices. Bind each one that is found. If |
| 947 | * devices are already bound that match the scanned devices, just update the |
| 948 | * child data so that the device can be used correctly (this happens when |
| 949 | * the device tree describes devices we expect to see on the bus). |
| 950 | * |
| 951 | * Devices that are bound in this way will use a generic PCI driver which |
| 952 | * does nothing. The device can still be accessed but will not provide any |
| 953 | * driver interface. |
| 954 | * |
| 955 | * @bus: Bus containing devices to bind |
| 956 | * @return 0 if OK, -ve on error |
| 957 | */ |
| 958 | int pci_bind_bus_devices(struct udevice *bus); |
| 959 | |
| 960 | /** |
| 961 | * pci_auto_config_devices() - configure bus devices ready for use |
| 962 | * |
| 963 | * This works through all devices on a bus by scanning the driver model |
| 964 | * data structures (normally these have been set up by pci_bind_bus_devices() |
| 965 | * earlier). |
| 966 | * |
| 967 | * Space is allocated for each PCI base address register (BAR) so that the |
| 968 | * devices are mapped into memory and I/O space ready for use. |
| 969 | * |
| 970 | * @bus: Bus containing devices to bind |
| 971 | * @return 0 if OK, -ve on error |
| 972 | */ |
| 973 | int pci_auto_config_devices(struct udevice *bus); |
| 974 | |
| 975 | /** |
Simon Glass | 84283d5 | 2015-11-29 13:17:48 -0700 | [diff] [blame] | 976 | * dm_pci_bus_find_bdf() - Find a device given its PCI bus address |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 977 | * |
| 978 | * @bdf: PCI device address: bus, device and function -see PCI_BDF() |
| 979 | * @devp: Returns the device for this address, if found |
| 980 | * @return 0 if OK, -ENODEV if not found |
| 981 | */ |
Simon Glass | 84283d5 | 2015-11-29 13:17:48 -0700 | [diff] [blame] | 982 | int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 983 | |
| 984 | /** |
| 985 | * pci_bus_find_devfn() - Find a device on a bus |
| 986 | * |
| 987 | * @find_devfn: PCI device address (device and function only) |
| 988 | * @devp: Returns the device for this address, if found |
| 989 | * @return 0 if OK, -ENODEV if not found |
| 990 | */ |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 991 | int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn, |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 992 | struct udevice **devp); |
| 993 | |
| 994 | /** |
Simon Glass | 04c8b6a | 2015-08-10 07:05:04 -0600 | [diff] [blame] | 995 | * pci_find_first_device() - return the first available PCI device |
| 996 | * |
| 997 | * This function and pci_find_first_device() allow iteration through all |
| 998 | * available PCI devices on all buses. Assuming there are any, this will |
| 999 | * return the first one. |
| 1000 | * |
| 1001 | * @devp: Set to the first available device, or NULL if no more are left |
| 1002 | * or we got an error |
| 1003 | * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) |
| 1004 | */ |
| 1005 | int pci_find_first_device(struct udevice **devp); |
| 1006 | |
| 1007 | /** |
| 1008 | * pci_find_next_device() - return the next available PCI device |
| 1009 | * |
| 1010 | * Finds the next available PCI device after the one supplied, or sets @devp |
| 1011 | * to NULL if there are no more. |
| 1012 | * |
| 1013 | * @devp: On entry, the last device returned. Set to the next available |
| 1014 | * device, or NULL if no more are left or we got an error |
| 1015 | * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) |
| 1016 | */ |
| 1017 | int pci_find_next_device(struct udevice **devp); |
| 1018 | |
| 1019 | /** |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1020 | * pci_get_ff() - Returns a mask for the given access size |
| 1021 | * |
| 1022 | * @size: Access size |
| 1023 | * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for |
| 1024 | * PCI_SIZE_32 |
| 1025 | */ |
| 1026 | int pci_get_ff(enum pci_size_t size); |
| 1027 | |
| 1028 | /** |
| 1029 | * pci_bus_find_devices () - Find devices on a bus |
| 1030 | * |
| 1031 | * @bus: Bus to search |
| 1032 | * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record |
| 1033 | * @indexp: Pointer to device index to find. To find the first matching |
| 1034 | * device, pass 0; to find the second, pass 1, etc. This |
| 1035 | * parameter is decremented for each non-matching device so |
| 1036 | * can be called repeatedly. |
| 1037 | * @devp: Returns matching device if found |
| 1038 | * @return 0 if found, -ENODEV if not |
| 1039 | */ |
Simon Glass | 3f7dc6e | 2021-06-27 17:50:56 -0600 | [diff] [blame] | 1040 | int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids, |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1041 | int *indexp, struct udevice **devp); |
| 1042 | |
| 1043 | /** |
| 1044 | * pci_find_device_id() - Find a device on any bus |
| 1045 | * |
| 1046 | * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record |
| 1047 | * @index: Index number of device to find, 0 for the first match, 1 for |
| 1048 | * the second, etc. |
| 1049 | * @devp: Returns matching device if found |
| 1050 | * @return 0 if found, -ENODEV if not |
| 1051 | */ |
Simon Glass | 3f7dc6e | 2021-06-27 17:50:56 -0600 | [diff] [blame] | 1052 | int pci_find_device_id(const struct pci_device_id *ids, int index, |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1053 | struct udevice **devp); |
| 1054 | |
| 1055 | /** |
| 1056 | * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices |
| 1057 | * |
| 1058 | * This probes the given bus which causes it to be scanned for devices. The |
| 1059 | * devices will be bound but not probed. |
| 1060 | * |
| 1061 | * @hose specifies the PCI hose that will be used for the scan. This is |
| 1062 | * always a top-level bus with uclass UCLASS_PCI. The bus to scan is |
| 1063 | * in @bdf, and is a subordinate bus reachable from @hose. |
| 1064 | * |
| 1065 | * @hose: PCI hose to scan |
| 1066 | * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) |
| 1067 | * @return 0 if OK, -ve on error |
| 1068 | */ |
Simon Glass | 37a3f94b | 2015-11-29 13:17:49 -0700 | [diff] [blame] | 1069 | int dm_pci_hose_probe_bus(struct udevice *bus); |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1070 | |
| 1071 | /** |
| 1072 | * pci_bus_read_config() - Read a configuration value from a device |
| 1073 | * |
| 1074 | * TODO(sjg@chromium.org): We should be able to pass just a device and have |
| 1075 | * it do the right thing. It would be good to have that function also. |
| 1076 | * |
| 1077 | * @bus: Bus to read from |
| 1078 | * @bdf: PCI device address: bus, device and function -see PCI_BDF() |
Simon Glass | 0d0f831 | 2016-03-06 19:27:53 -0700 | [diff] [blame] | 1079 | * @offset: Register offset to read |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1080 | * @valuep: Place to put the returned value |
| 1081 | * @size: Access size |
| 1082 | * @return 0 if OK, -ve on error |
| 1083 | */ |
Simon Glass | c92aac1 | 2020-01-27 08:49:38 -0700 | [diff] [blame] | 1084 | int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset, |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1085 | unsigned long *valuep, enum pci_size_t size); |
| 1086 | |
| 1087 | /** |
| 1088 | * pci_bus_write_config() - Write a configuration value to a device |
| 1089 | * |
| 1090 | * @bus: Bus to write from |
| 1091 | * @bdf: PCI device address: bus, device and function -see PCI_BDF() |
Simon Glass | 0d0f831 | 2016-03-06 19:27:53 -0700 | [diff] [blame] | 1092 | * @offset: Register offset to write |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1093 | * @value: Value to write |
| 1094 | * @size: Access size |
| 1095 | * @return 0 if OK, -ve on error |
| 1096 | */ |
| 1097 | int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, |
| 1098 | unsigned long value, enum pci_size_t size); |
| 1099 | |
Simon Glass | 94ef242 | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 1100 | /** |
Simon Glass | 9cec2df | 2016-03-06 19:27:52 -0700 | [diff] [blame] | 1101 | * pci_bus_clrset_config32() - Update a configuration value for a device |
| 1102 | * |
| 1103 | * The register at @offset is updated to (oldvalue & ~clr) | set. |
| 1104 | * |
| 1105 | * @bus: Bus to access |
| 1106 | * @bdf: PCI device address: bus, device and function -see PCI_BDF() |
| 1107 | * @offset: Register offset to update |
| 1108 | * @clr: Bits to clear |
| 1109 | * @set: Bits to set |
| 1110 | * @return 0 if OK, -ve on error |
| 1111 | */ |
| 1112 | int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, |
| 1113 | u32 clr, u32 set); |
| 1114 | |
| 1115 | /** |
Simon Glass | 94ef242 | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 1116 | * Driver model PCI config access functions. Use these in preference to others |
| 1117 | * when you have a valid device |
| 1118 | */ |
Simon Glass | c92aac1 | 2020-01-27 08:49:38 -0700 | [diff] [blame] | 1119 | int dm_pci_read_config(const struct udevice *dev, int offset, |
| 1120 | unsigned long *valuep, enum pci_size_t size); |
Simon Glass | 94ef242 | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 1121 | |
Simon Glass | c92aac1 | 2020-01-27 08:49:38 -0700 | [diff] [blame] | 1122 | int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep); |
| 1123 | int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep); |
| 1124 | int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep); |
Simon Glass | 94ef242 | 2015-08-10 07:05:03 -0600 | [diff] [blame] | 1125 | |
| 1126 | int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, |
| 1127 | enum pci_size_t size); |
| 1128 | |
| 1129 | int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); |
| 1130 | int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); |
| 1131 | int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); |
| 1132 | |
Simon Glass | 9cec2df | 2016-03-06 19:27:52 -0700 | [diff] [blame] | 1133 | /** |
| 1134 | * These permit convenient read/modify/write on PCI configuration. The |
| 1135 | * register is updated to (oldvalue & ~clr) | set. |
| 1136 | */ |
| 1137 | int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); |
| 1138 | int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); |
| 1139 | int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); |
| 1140 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1141 | /* |
| 1142 | * The following functions provide access to the above without needing the |
| 1143 | * size parameter. We are trying to encourage the use of the 8/16/32-style |
| 1144 | * functions, rather than byte/word/dword. But both are supported. |
| 1145 | */ |
| 1146 | int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); |
Bin Meng | 0226859 | 2016-02-02 05:58:07 -0800 | [diff] [blame] | 1147 | int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); |
| 1148 | int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); |
| 1149 | int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); |
| 1150 | int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); |
| 1151 | int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1152 | |
Tuomas Tynkkynen | 8cce4cf | 2017-09-19 23:18:03 +0300 | [diff] [blame] | 1153 | /** |
| 1154 | * pci_generic_mmap_write_config() - Generic helper for writing to |
| 1155 | * memory-mapped PCI configuration space. |
| 1156 | * @bus: Pointer to the PCI bus |
| 1157 | * @addr_f: Callback for calculating the config space address |
| 1158 | * @bdf: Identifies the PCI device to access |
| 1159 | * @offset: The offset into the device's configuration space |
| 1160 | * @value: The value to write |
| 1161 | * @size: Indicates the size of access to perform |
| 1162 | * |
| 1163 | * Write the value @value of size @size from offset @offset within the |
| 1164 | * configuration space of the device identified by the bus, device & function |
| 1165 | * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is |
| 1166 | * responsible for calculating the CPU address of the respective configuration |
| 1167 | * space offset. |
| 1168 | * |
| 1169 | * Return: 0 on success, else -EINVAL |
| 1170 | */ |
| 1171 | int pci_generic_mmap_write_config( |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 1172 | const struct udevice *bus, |
| 1173 | int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset, |
| 1174 | void **addrp), |
Tuomas Tynkkynen | 8cce4cf | 2017-09-19 23:18:03 +0300 | [diff] [blame] | 1175 | pci_dev_t bdf, |
| 1176 | uint offset, |
| 1177 | ulong value, |
| 1178 | enum pci_size_t size); |
| 1179 | |
| 1180 | /** |
| 1181 | * pci_generic_mmap_read_config() - Generic helper for reading from |
| 1182 | * memory-mapped PCI configuration space. |
| 1183 | * @bus: Pointer to the PCI bus |
| 1184 | * @addr_f: Callback for calculating the config space address |
| 1185 | * @bdf: Identifies the PCI device to access |
| 1186 | * @offset: The offset into the device's configuration space |
| 1187 | * @valuep: A pointer at which to store the read value |
| 1188 | * @size: Indicates the size of access to perform |
| 1189 | * |
| 1190 | * Read a value of size @size from offset @offset within the configuration |
| 1191 | * space of the device identified by the bus, device & function numbers in @bdf |
| 1192 | * on the PCI bus @bus. The callback function @addr_f is responsible for |
| 1193 | * calculating the CPU address of the respective configuration space offset. |
| 1194 | * |
| 1195 | * Return: 0 on success, else -EINVAL |
| 1196 | */ |
| 1197 | int pci_generic_mmap_read_config( |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 1198 | const struct udevice *bus, |
| 1199 | int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset, |
| 1200 | void **addrp), |
Tuomas Tynkkynen | 8cce4cf | 2017-09-19 23:18:03 +0300 | [diff] [blame] | 1201 | pci_dev_t bdf, |
| 1202 | uint offset, |
| 1203 | ulong *valuep, |
| 1204 | enum pci_size_t size); |
| 1205 | |
Suneel Garapati | 13822f7 | 2019-10-19 16:07:20 -0700 | [diff] [blame] | 1206 | #if defined(CONFIG_PCI_SRIOV) |
| 1207 | /** |
| 1208 | * pci_sriov_init() - Scan Virtual Function devices |
| 1209 | * |
| 1210 | * @pdev: Physical Function udevice handle |
| 1211 | * @vf_en: Number of Virtual Function devices to enable |
| 1212 | * @return 0 on success, -ve on error |
| 1213 | */ |
| 1214 | int pci_sriov_init(struct udevice *pdev, int vf_en); |
| 1215 | |
| 1216 | /** |
| 1217 | * pci_sriov_get_totalvfs() - Get total available Virtual Function devices |
| 1218 | * |
| 1219 | * @pdev: Physical Function udevice handle |
| 1220 | * @return count on success, -ve on error |
| 1221 | */ |
| 1222 | int pci_sriov_get_totalvfs(struct udevice *pdev); |
| 1223 | #endif |
| 1224 | |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 1225 | #ifdef CONFIG_DM_PCI_COMPAT |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1226 | /* Compatibility with old naming */ |
| 1227 | static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, |
| 1228 | u32 value) |
| 1229 | { |
| 1230 | return pci_write_config32(pcidev, offset, value); |
| 1231 | } |
| 1232 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1233 | /* Compatibility with old naming */ |
| 1234 | static inline int pci_write_config_word(pci_dev_t pcidev, int offset, |
| 1235 | u16 value) |
| 1236 | { |
| 1237 | return pci_write_config16(pcidev, offset, value); |
| 1238 | } |
| 1239 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1240 | /* Compatibility with old naming */ |
| 1241 | static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, |
| 1242 | u8 value) |
| 1243 | { |
| 1244 | return pci_write_config8(pcidev, offset, value); |
| 1245 | } |
| 1246 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1247 | /* Compatibility with old naming */ |
| 1248 | static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, |
| 1249 | u32 *valuep) |
| 1250 | { |
| 1251 | return pci_read_config32(pcidev, offset, valuep); |
| 1252 | } |
| 1253 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1254 | /* Compatibility with old naming */ |
| 1255 | static inline int pci_read_config_word(pci_dev_t pcidev, int offset, |
| 1256 | u16 *valuep) |
| 1257 | { |
| 1258 | return pci_read_config16(pcidev, offset, valuep); |
| 1259 | } |
| 1260 | |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1261 | /* Compatibility with old naming */ |
| 1262 | static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, |
| 1263 | u8 *valuep) |
| 1264 | { |
| 1265 | return pci_read_config8(pcidev, offset, valuep); |
| 1266 | } |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 1267 | #endif /* CONFIG_DM_PCI_COMPAT */ |
| 1268 | |
| 1269 | /** |
| 1270 | * dm_pciauto_config_device() - configure a device ready for use |
| 1271 | * |
| 1272 | * Space is allocated for each PCI base address register (BAR) so that the |
| 1273 | * devices are mapped into memory and I/O space ready for use. |
| 1274 | * |
| 1275 | * @dev: Device to configure |
| 1276 | * @return 0 if OK, -ve on error |
| 1277 | */ |
| 1278 | int dm_pciauto_config_device(struct udevice *dev); |
| 1279 | |
Simon Glass | d9e90bb | 2015-03-05 12:25:28 -0700 | [diff] [blame] | 1280 | /** |
Simon Glass | 27a733f | 2015-11-19 20:26:59 -0700 | [diff] [blame] | 1281 | * pci_conv_32_to_size() - convert a 32-bit read value to the given size |
| 1282 | * |
| 1283 | * Some PCI buses must always perform 32-bit reads. The data must then be |
| 1284 | * shifted and masked to reflect the required access size and offset. This |
| 1285 | * function performs this transformation. |
| 1286 | * |
| 1287 | * @value: Value to transform (32-bit value read from @offset & ~3) |
| 1288 | * @offset: Register offset that was read |
| 1289 | * @size: Required size of the result |
| 1290 | * @return the value that would have been obtained if the read had been |
| 1291 | * performed at the given offset with the correct size |
| 1292 | */ |
| 1293 | ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); |
| 1294 | |
| 1295 | /** |
| 1296 | * pci_conv_size_to_32() - update a 32-bit value to prepare for a write |
| 1297 | * |
| 1298 | * Some PCI buses must always perform 32-bit writes. To emulate a smaller |
| 1299 | * write the old 32-bit data must be read, updated with the required new data |
| 1300 | * and written back as a 32-bit value. This function performs the |
| 1301 | * transformation from the old value to the new value. |
| 1302 | * |
| 1303 | * @value: Value to transform (32-bit value read from @offset & ~3) |
| 1304 | * @offset: Register offset that should be written |
| 1305 | * @size: Required size of the write |
| 1306 | * @return the value that should be written as a 32-bit access to @offset & ~3. |
| 1307 | */ |
| 1308 | ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, |
| 1309 | enum pci_size_t size); |
| 1310 | |
| 1311 | /** |
Simon Glass | 6256d67 | 2015-11-19 20:27:00 -0700 | [diff] [blame] | 1312 | * pci_get_controller() - obtain the controller to use for a bus |
| 1313 | * |
| 1314 | * @dev: Device to check |
| 1315 | * @return pointer to the controller device for this bus |
| 1316 | */ |
| 1317 | struct udevice *pci_get_controller(struct udevice *dev); |
| 1318 | |
| 1319 | /** |
Simon Glass | dcdc012 | 2015-11-19 20:27:01 -0700 | [diff] [blame] | 1320 | * pci_get_regions() - obtain pointers to all the region types |
| 1321 | * |
| 1322 | * @dev: Device to check |
| 1323 | * @iop: Returns a pointer to the I/O region, or NULL if none |
| 1324 | * @memp: Returns a pointer to the memory region, or NULL if none |
| 1325 | * @prefp: Returns a pointer to the pre-fetch region, or NULL if none |
| 1326 | * @return the number of non-NULL regions returned, normally 3 |
| 1327 | */ |
| 1328 | int pci_get_regions(struct udevice *dev, struct pci_region **iop, |
| 1329 | struct pci_region **memp, struct pci_region **prefp); |
Rayagonda Kokatanur | cdc7ed3 | 2020-05-12 13:29:49 +0530 | [diff] [blame] | 1330 | int |
| 1331 | pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index); |
Simon Glass | dcdc012 | 2015-11-19 20:27:01 -0700 | [diff] [blame] | 1332 | /** |
Simon Glass | e2b6b56 | 2016-01-18 20:19:15 -0700 | [diff] [blame] | 1333 | * dm_pci_write_bar32() - Write the address of a BAR |
| 1334 | * |
| 1335 | * This writes a raw address to a bar |
| 1336 | * |
| 1337 | * @dev: PCI device to update |
| 1338 | * @barnum: BAR number (0-5) |
| 1339 | * @addr: BAR address |
| 1340 | */ |
| 1341 | void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); |
| 1342 | |
| 1343 | /** |
Simon Glass | 3452cb1 | 2015-11-29 13:17:53 -0700 | [diff] [blame] | 1344 | * dm_pci_read_bar32() - read a base address register from a device |
| 1345 | * |
| 1346 | * @dev: Device to check |
| 1347 | * @barnum: Bar number to read (numbered from 0) |
| 1348 | * @return: value of BAR |
| 1349 | */ |
Simon Glass | c92aac1 | 2020-01-27 08:49:38 -0700 | [diff] [blame] | 1350 | u32 dm_pci_read_bar32(const struct udevice *dev, int barnum); |
Simon Glass | 3452cb1 | 2015-11-29 13:17:53 -0700 | [diff] [blame] | 1351 | |
| 1352 | /** |
Simon Glass | c5f053b | 2015-11-29 13:18:03 -0700 | [diff] [blame] | 1353 | * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address |
| 1354 | * |
| 1355 | * @dev: Device containing the PCI address |
| 1356 | * @addr: PCI address to convert |
| 1357 | * @flags: Flags for the region type (PCI_REGION_...) |
| 1358 | * @return physical address corresponding to that PCI bus address |
| 1359 | */ |
| 1360 | phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, |
| 1361 | unsigned long flags); |
| 1362 | |
| 1363 | /** |
| 1364 | * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address |
| 1365 | * |
| 1366 | * @dev: Device containing the bus address |
| 1367 | * @addr: Physical address to convert |
| 1368 | * @flags: Flags for the region type (PCI_REGION_...) |
| 1369 | * @return PCI bus address corresponding to that physical address |
| 1370 | */ |
| 1371 | pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, |
| 1372 | unsigned long flags); |
| 1373 | |
| 1374 | /** |
| 1375 | * dm_pci_map_bar() - get a virtual address associated with a BAR region |
| 1376 | * |
| 1377 | * Looks up a base address register and finds the physical memory address |
Alex Marginean | b8514f3 | 2019-06-07 11:24:22 +0300 | [diff] [blame] | 1378 | * that corresponds to it. |
| 1379 | * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on |
| 1380 | * type 1 functions. |
Alex Marginean | 1c934a6 | 2019-06-07 11:24:23 +0300 | [diff] [blame] | 1381 | * Can also be used on type 0 functions that support Enhanced Allocation for |
| 1382 | * 32b/64b BARs. Note that duplicate BEI entries are not supported. |
Simon Glass | c5f053b | 2015-11-29 13:18:03 -0700 | [diff] [blame] | 1383 | * |
| 1384 | * @dev: Device to check |
Alex Marginean | b8514f3 | 2019-06-07 11:24:22 +0300 | [diff] [blame] | 1385 | * @bar: Bar register offset (PCI_BASE_ADDRESS_...) |
Simon Glass | c5f053b | 2015-11-29 13:18:03 -0700 | [diff] [blame] | 1386 | * @flags: Flags for the region type (PCI_REGION_...) |
Alex Marginean | b8514f3 | 2019-06-07 11:24:22 +0300 | [diff] [blame] | 1387 | * @return: pointer to the virtual address to use or 0 on error |
Simon Glass | c5f053b | 2015-11-29 13:18:03 -0700 | [diff] [blame] | 1388 | */ |
| 1389 | void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); |
| 1390 | |
Bin Meng | a7366f0 | 2018-08-03 01:14:52 -0700 | [diff] [blame] | 1391 | /** |
Bin Meng | 631f348 | 2018-10-15 02:21:21 -0700 | [diff] [blame] | 1392 | * dm_pci_find_next_capability() - find a capability starting from an offset |
| 1393 | * |
| 1394 | * Tell if a device supports a given PCI capability. Returns the |
| 1395 | * address of the requested capability structure within the device's |
| 1396 | * PCI configuration space or 0 in case the device does not support it. |
| 1397 | * |
| 1398 | * Possible values for @cap: |
| 1399 | * |
| 1400 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
| 1401 | * %PCI_CAP_ID_PCIX PCI-X |
| 1402 | * %PCI_CAP_ID_EXP PCI Express |
| 1403 | * %PCI_CAP_ID_MSIX MSI-X |
| 1404 | * |
| 1405 | * See PCI_CAP_ID_xxx for the complete capability ID codes. |
| 1406 | * |
| 1407 | * @dev: PCI device to query |
| 1408 | * @start: offset to start from |
| 1409 | * @cap: capability code |
| 1410 | * @return: capability address or 0 if not supported |
| 1411 | */ |
| 1412 | int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap); |
| 1413 | |
| 1414 | /** |
Bin Meng | a7366f0 | 2018-08-03 01:14:52 -0700 | [diff] [blame] | 1415 | * dm_pci_find_capability() - find a capability |
| 1416 | * |
| 1417 | * Tell if a device supports a given PCI capability. Returns the |
| 1418 | * address of the requested capability structure within the device's |
| 1419 | * PCI configuration space or 0 in case the device does not support it. |
| 1420 | * |
| 1421 | * Possible values for @cap: |
| 1422 | * |
| 1423 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
| 1424 | * %PCI_CAP_ID_PCIX PCI-X |
| 1425 | * %PCI_CAP_ID_EXP PCI Express |
| 1426 | * %PCI_CAP_ID_MSIX MSI-X |
| 1427 | * |
| 1428 | * See PCI_CAP_ID_xxx for the complete capability ID codes. |
| 1429 | * |
| 1430 | * @dev: PCI device to query |
| 1431 | * @cap: capability code |
| 1432 | * @return: capability address or 0 if not supported |
| 1433 | */ |
| 1434 | int dm_pci_find_capability(struct udevice *dev, int cap); |
| 1435 | |
| 1436 | /** |
Bin Meng | 631f348 | 2018-10-15 02:21:21 -0700 | [diff] [blame] | 1437 | * dm_pci_find_next_ext_capability() - find an extended capability |
| 1438 | * starting from an offset |
| 1439 | * |
| 1440 | * Tell if a device supports a given PCI express extended capability. |
| 1441 | * Returns the address of the requested extended capability structure |
| 1442 | * within the device's PCI configuration space or 0 in case the device |
| 1443 | * does not support it. |
| 1444 | * |
| 1445 | * Possible values for @cap: |
| 1446 | * |
| 1447 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting |
| 1448 | * %PCI_EXT_CAP_ID_VC Virtual Channel |
| 1449 | * %PCI_EXT_CAP_ID_DSN Device Serial Number |
| 1450 | * %PCI_EXT_CAP_ID_PWR Power Budgeting |
| 1451 | * |
| 1452 | * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. |
| 1453 | * |
| 1454 | * @dev: PCI device to query |
| 1455 | * @start: offset to start from |
| 1456 | * @cap: extended capability code |
| 1457 | * @return: extended capability address or 0 if not supported |
| 1458 | */ |
| 1459 | int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap); |
| 1460 | |
| 1461 | /** |
Bin Meng | a7366f0 | 2018-08-03 01:14:52 -0700 | [diff] [blame] | 1462 | * dm_pci_find_ext_capability() - find an extended capability |
| 1463 | * |
| 1464 | * Tell if a device supports a given PCI express extended capability. |
| 1465 | * Returns the address of the requested extended capability structure |
| 1466 | * within the device's PCI configuration space or 0 in case the device |
| 1467 | * does not support it. |
| 1468 | * |
| 1469 | * Possible values for @cap: |
| 1470 | * |
| 1471 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting |
| 1472 | * %PCI_EXT_CAP_ID_VC Virtual Channel |
| 1473 | * %PCI_EXT_CAP_ID_DSN Device Serial Number |
| 1474 | * %PCI_EXT_CAP_ID_PWR Power Budgeting |
| 1475 | * |
| 1476 | * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. |
| 1477 | * |
| 1478 | * @dev: PCI device to query |
| 1479 | * @cap: extended capability code |
| 1480 | * @return: extended capability address or 0 if not supported |
| 1481 | */ |
| 1482 | int dm_pci_find_ext_capability(struct udevice *dev, int cap); |
| 1483 | |
Alex Marginean | 09467d3 | 2019-06-07 11:24:25 +0300 | [diff] [blame] | 1484 | /** |
| 1485 | * dm_pci_flr() - Perform FLR if the device suppoorts it |
| 1486 | * |
| 1487 | * @dev: PCI device to reset |
| 1488 | * @return: 0 if OK, -ENOENT if FLR is not supported by dev |
| 1489 | */ |
| 1490 | int dm_pci_flr(struct udevice *dev); |
| 1491 | |
Simon Glass | c5f053b | 2015-11-29 13:18:03 -0700 | [diff] [blame] | 1492 | #define dm_pci_virt_to_bus(dev, addr, flags) \ |
| 1493 | dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) |
| 1494 | #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ |
| 1495 | map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \ |
| 1496 | (len), (map_flags)) |
| 1497 | |
| 1498 | #define dm_pci_phys_to_mem(dev, addr) \ |
| 1499 | dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) |
| 1500 | #define dm_pci_mem_to_phys(dev, addr) \ |
| 1501 | dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) |
| 1502 | #define dm_pci_phys_to_io(dev, addr) \ |
| 1503 | dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO) |
| 1504 | #define dm_pci_io_to_phys(dev, addr) \ |
| 1505 | dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO) |
| 1506 | |
| 1507 | #define dm_pci_virt_to_mem(dev, addr) \ |
| 1508 | dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) |
| 1509 | #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ |
| 1510 | dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) |
| 1511 | #define dm_pci_virt_to_io(dev, addr) \ |
Simon Glass | 0d0f831 | 2016-03-06 19:27:53 -0700 | [diff] [blame] | 1512 | dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) |
Simon Glass | c5f053b | 2015-11-29 13:18:03 -0700 | [diff] [blame] | 1513 | #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ |
Simon Glass | 0d0f831 | 2016-03-06 19:27:53 -0700 | [diff] [blame] | 1514 | dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) |
Simon Glass | c5f053b | 2015-11-29 13:18:03 -0700 | [diff] [blame] | 1515 | |
| 1516 | /** |
Simon Glass | 70e0c58 | 2015-11-29 13:17:50 -0700 | [diff] [blame] | 1517 | * dm_pci_find_device() - find a device by vendor/device ID |
| 1518 | * |
| 1519 | * @vendor: Vendor ID |
| 1520 | * @device: Device ID |
| 1521 | * @index: 0 to find the first match, 1 for second, etc. |
| 1522 | * @devp: Returns pointer to the device, if found |
| 1523 | * @return 0 if found, -ve on error |
| 1524 | */ |
| 1525 | int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, |
| 1526 | struct udevice **devp); |
| 1527 | |
| 1528 | /** |
Simon Glass | b639d51 | 2015-11-29 13:17:52 -0700 | [diff] [blame] | 1529 | * dm_pci_find_class() - find a device by class |
| 1530 | * |
| 1531 | * @find_class: 3-byte (24-bit) class value to find |
| 1532 | * @index: 0 to find the first match, 1 for second, etc. |
| 1533 | * @devp: Returns pointer to the device, if found |
| 1534 | * @return 0 if found, -ve on error |
| 1535 | */ |
| 1536 | int dm_pci_find_class(uint find_class, int index, struct udevice **devp); |
| 1537 | |
| 1538 | /** |
Simon Glass | a51fd07 | 2019-09-21 14:32:41 -0600 | [diff] [blame] | 1539 | * struct pci_emul_uc_priv - holds info about an emulator device |
| 1540 | * |
| 1541 | * There is always at most one emulator per client |
| 1542 | * |
| 1543 | * @client: Client device if any, else NULL |
| 1544 | */ |
| 1545 | struct pci_emul_uc_priv { |
| 1546 | struct udevice *client; |
| 1547 | }; |
| 1548 | |
| 1549 | /** |
Simon Glass | d9e90bb | 2015-03-05 12:25:28 -0700 | [diff] [blame] | 1550 | * struct dm_pci_emul_ops - PCI device emulator operations |
| 1551 | */ |
| 1552 | struct dm_pci_emul_ops { |
| 1553 | /** |
Simon Glass | d9e90bb | 2015-03-05 12:25:28 -0700 | [diff] [blame] | 1554 | * read_config() - Read a PCI configuration value |
| 1555 | * |
| 1556 | * @dev: Emulated device to read from |
| 1557 | * @offset: Byte offset within the device's configuration space |
| 1558 | * @valuep: Place to put the returned value |
| 1559 | * @size: Access size |
| 1560 | * @return 0 if OK, -ve on error |
| 1561 | */ |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 1562 | int (*read_config)(const struct udevice *dev, uint offset, |
| 1563 | ulong *valuep, enum pci_size_t size); |
Simon Glass | d9e90bb | 2015-03-05 12:25:28 -0700 | [diff] [blame] | 1564 | /** |
| 1565 | * write_config() - Write a PCI configuration value |
| 1566 | * |
| 1567 | * @dev: Emulated device to write to |
| 1568 | * @offset: Byte offset within the device's configuration space |
| 1569 | * @value: Value to write |
| 1570 | * @size: Access size |
| 1571 | * @return 0 if OK, -ve on error |
| 1572 | */ |
| 1573 | int (*write_config)(struct udevice *dev, uint offset, ulong value, |
| 1574 | enum pci_size_t size); |
| 1575 | /** |
| 1576 | * read_io() - Read a PCI I/O value |
| 1577 | * |
| 1578 | * @dev: Emulated device to read from |
| 1579 | * @addr: I/O address to read |
| 1580 | * @valuep: Place to put the returned value |
| 1581 | * @size: Access size |
| 1582 | * @return 0 if OK, -ENOENT if @addr is not mapped by this device, |
| 1583 | * other -ve value on error |
| 1584 | */ |
| 1585 | int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, |
| 1586 | enum pci_size_t size); |
| 1587 | /** |
| 1588 | * write_io() - Write a PCI I/O value |
| 1589 | * |
| 1590 | * @dev: Emulated device to write from |
| 1591 | * @addr: I/O address to write |
| 1592 | * @value: Value to write |
| 1593 | * @size: Access size |
| 1594 | * @return 0 if OK, -ENOENT if @addr is not mapped by this device, |
| 1595 | * other -ve value on error |
| 1596 | */ |
| 1597 | int (*write_io)(struct udevice *dev, unsigned int addr, |
| 1598 | ulong value, enum pci_size_t size); |
| 1599 | /** |
| 1600 | * map_physmem() - Map a device into sandbox memory |
| 1601 | * |
| 1602 | * @dev: Emulated device to map |
| 1603 | * @addr: Memory address, normally corresponding to a PCI BAR. |
| 1604 | * The device should have been configured to have a BAR |
| 1605 | * at this address. |
| 1606 | * @lenp: On entry, the size of the area to map, On exit it is |
| 1607 | * updated to the size actually mapped, which may be less |
| 1608 | * if the device has less space |
| 1609 | * @ptrp: Returns a pointer to the mapped address. The device's |
| 1610 | * space can be accessed as @lenp bytes starting here |
| 1611 | * @return 0 if OK, -ENOENT if @addr is not mapped by this device, |
| 1612 | * other -ve value on error |
| 1613 | */ |
| 1614 | int (*map_physmem)(struct udevice *dev, phys_addr_t addr, |
| 1615 | unsigned long *lenp, void **ptrp); |
| 1616 | /** |
| 1617 | * unmap_physmem() - undo a memory mapping |
| 1618 | * |
| 1619 | * This must be called after map_physmem() to undo the mapping. |
| 1620 | * Some devices can use this to check what has been written into |
| 1621 | * their mapped memory and perform an operations they require on it. |
| 1622 | * In this way, map/unmap can be used as a sort of handshake between |
| 1623 | * the emulated device and its users. |
| 1624 | * |
| 1625 | * @dev: Emuated device to unmap |
| 1626 | * @vaddr: Mapped memory address, as passed to map_physmem() |
| 1627 | * @len: Size of area mapped, as returned by map_physmem() |
| 1628 | * @return 0 if OK, -ve on error |
| 1629 | */ |
| 1630 | int (*unmap_physmem)(struct udevice *dev, const void *vaddr, |
| 1631 | unsigned long len); |
| 1632 | }; |
| 1633 | |
| 1634 | /* Get access to a PCI device emulator's operations */ |
| 1635 | #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) |
| 1636 | |
| 1637 | /** |
| 1638 | * sandbox_pci_get_emul() - Get the emulation device for a PCI device |
| 1639 | * |
| 1640 | * Searches for a suitable emulator for the given PCI bus device |
| 1641 | * |
| 1642 | * @bus: PCI bus to search |
| 1643 | * @find_devfn: PCI device and function address (PCI_DEVFN()) |
Bin Meng | 156bc6f | 2018-08-03 01:14:45 -0700 | [diff] [blame] | 1644 | * @containerp: Returns container device if found |
Simon Glass | d9e90bb | 2015-03-05 12:25:28 -0700 | [diff] [blame] | 1645 | * @emulp: Returns emulated device if found |
| 1646 | * @return 0 if found, -ENODEV if not found |
| 1647 | */ |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 1648 | int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn, |
Bin Meng | 156bc6f | 2018-08-03 01:14:45 -0700 | [diff] [blame] | 1649 | struct udevice **containerp, struct udevice **emulp); |
Simon Glass | d9e90bb | 2015-03-05 12:25:28 -0700 | [diff] [blame] | 1650 | |
Stefan Roese | a74eb55 | 2019-01-25 11:52:42 +0100 | [diff] [blame] | 1651 | /** |
Simon Glass | a51fd07 | 2019-09-21 14:32:41 -0600 | [diff] [blame] | 1652 | * sandbox_pci_get_client() - Find the client for an emulation device |
| 1653 | * |
| 1654 | * @emul: Emulation device to check |
| 1655 | * @devp: Returns the client device emulated by this device |
| 1656 | * @return 0 if OK, -ENOENT if the device has no client yet |
| 1657 | */ |
| 1658 | int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp); |
| 1659 | |
Tim Harvey | 4c57bf7 | 2021-04-16 14:53:47 -0700 | [diff] [blame] | 1660 | /** |
| 1661 | * board_pci_fixup_dev() - Board callback for PCI device fixups |
| 1662 | * |
| 1663 | * @bus: PCI bus |
| 1664 | * @dev: PCI device |
| 1665 | */ |
| 1666 | extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev); |
| 1667 | |
Simon Glass | 318d71c | 2015-07-06 16:47:44 -0600 | [diff] [blame] | 1668 | /** |
| 1669 | * PCI_DEVICE - macro used to describe a specific pci device |
| 1670 | * @vend: the 16 bit PCI Vendor ID |
| 1671 | * @dev: the 16 bit PCI Device ID |
| 1672 | * |
| 1673 | * This macro is used to create a struct pci_device_id that matches a |
| 1674 | * specific device. The subvendor and subdevice fields will be set to |
| 1675 | * PCI_ANY_ID. |
| 1676 | */ |
| 1677 | #define PCI_DEVICE(vend, dev) \ |
| 1678 | .vendor = (vend), .device = (dev), \ |
| 1679 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
| 1680 | |
| 1681 | /** |
| 1682 | * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem |
| 1683 | * @vend: the 16 bit PCI Vendor ID |
| 1684 | * @dev: the 16 bit PCI Device ID |
| 1685 | * @subvend: the 16 bit PCI Subvendor ID |
| 1686 | * @subdev: the 16 bit PCI Subdevice ID |
| 1687 | * |
| 1688 | * This macro is used to create a struct pci_device_id that matches a |
| 1689 | * specific device with subsystem information. |
| 1690 | */ |
| 1691 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ |
| 1692 | .vendor = (vend), .device = (dev), \ |
| 1693 | .subvendor = (subvend), .subdevice = (subdev) |
| 1694 | |
| 1695 | /** |
| 1696 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class |
| 1697 | * @dev_class: the class, subclass, prog-if triple for this device |
| 1698 | * @dev_class_mask: the class mask for this device |
| 1699 | * |
| 1700 | * This macro is used to create a struct pci_device_id that matches a |
| 1701 | * specific PCI class. The vendor, device, subvendor, and subdevice |
| 1702 | * fields will be set to PCI_ANY_ID. |
| 1703 | */ |
| 1704 | #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ |
| 1705 | .class = (dev_class), .class_mask = (dev_class_mask), \ |
| 1706 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ |
| 1707 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
| 1708 | |
| 1709 | /** |
| 1710 | * PCI_VDEVICE - macro used to describe a specific pci device in short form |
| 1711 | * @vend: the vendor name |
| 1712 | * @dev: the 16 bit PCI Device ID |
| 1713 | * |
| 1714 | * This macro is used to create a struct pci_device_id that matches a |
| 1715 | * specific PCI device. The subvendor, and subdevice fields will be set |
| 1716 | * to PCI_ANY_ID. The macro allows the next field to follow as the device |
| 1717 | * private data. |
| 1718 | */ |
| 1719 | |
| 1720 | #define PCI_VDEVICE(vend, dev) \ |
| 1721 | .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ |
| 1722 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 |
| 1723 | |
| 1724 | /** |
| 1725 | * struct pci_driver_entry - Matches a driver to its pci_device_id list |
| 1726 | * @driver: Driver to use |
| 1727 | * @match: List of match records for this driver, terminated by {} |
| 1728 | */ |
| 1729 | struct pci_driver_entry { |
| 1730 | struct driver *driver; |
| 1731 | const struct pci_device_id *match; |
| 1732 | }; |
| 1733 | |
| 1734 | #define U_BOOT_PCI_DEVICE(__name, __match) \ |
| 1735 | ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ |
| 1736 | .driver = llsym(struct driver, __name, driver), \ |
| 1737 | .match = __match, \ |
| 1738 | } |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1739 | |
Paul Burton | 162116e | 2013-11-08 11:18:47 +0000 | [diff] [blame] | 1740 | #endif /* __ASSEMBLY__ */ |
| 1741 | #endif /* _PCI_H */ |