Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> |
| 4 | * |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__ |
| 8 | #define __CONFIG_SOCFPGA_SOC64_COMMON_H__ |
| 9 | |
Siew Chin Lim | 142d9c0 | 2021-08-10 11:26:27 +0800 | [diff] [blame] | 10 | #include <asm/arch/base_addr_soc64.h> |
Siew Chin Lim | 954d599 | 2021-03-24 13:11:34 +0800 | [diff] [blame] | 11 | #include <asm/arch/handoff_soc64.h> |
Simon Glass | fb64e36 | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 12 | #include <linux/stringify.h> |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 13 | |
| 14 | /* |
| 15 | * U-Boot general configurations |
| 16 | */ |
| 17 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 18 | #define CONFIG_REMAKE_ELF |
| 19 | /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ |
| 20 | #define CPU_RELEASE_ADDR 0xFFD12210 |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 21 | |
| 22 | /* |
| 23 | * U-Boot console configurations |
| 24 | */ |
| 25 | #define CONFIG_SYS_MAXARGS 64 |
| 26 | #define CONFIG_SYS_CBSIZE 2048 |
| 27 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 28 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 29 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 30 | |
| 31 | /* Extend size of kernel image for uncompression */ |
| 32 | #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) |
| 33 | |
| 34 | /* |
| 35 | * U-Boot run time memory configurations |
| 36 | */ |
| 37 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 |
| 38 | #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 |
Chee Hong Ang | 25d45cb | 2020-12-24 18:21:09 +0800 | [diff] [blame] | 39 | #ifdef CONFIG_SPL_BUILD |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 40 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ |
| 41 | + CONFIG_SYS_INIT_RAM_SIZE \ |
Siew Chin Lim | 954d599 | 2021-03-24 13:11:34 +0800 | [diff] [blame] | 42 | - SOC64_HANDOFF_SIZE) |
Chee Hong Ang | 25d45cb | 2020-12-24 18:21:09 +0800 | [diff] [blame] | 43 | #else |
| 44 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \ |
| 45 | + 0x100000) |
| 46 | #endif |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 47 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * U-Boot environment configurations |
| 51 | */ |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 52 | |
| 53 | /* |
| 54 | * QSPI support |
| 55 | */ |
| 56 | #ifdef CONFIG_CADENCE_QSPI |
| 57 | /* Enable it if you want to use dual-stacked mode */ |
| 58 | /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ |
| 59 | |
| 60 | /* Flash device info */ |
| 61 | |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 62 | #ifndef CONFIG_SPL_BUILD |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 63 | #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" |
| 64 | #endif /* CONFIG_SPL_BUILD */ |
| 65 | |
| 66 | #ifndef __ASSEMBLY__ |
| 67 | unsigned int cm_get_qspi_controller_clk_hz(void); |
| 68 | #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() |
| 69 | #endif |
| 70 | |
| 71 | #endif /* CONFIG_CADENCE_QSPI */ |
| 72 | |
| 73 | /* |
Siew Chin Lim | 14b8a48 | 2021-03-01 20:04:14 +0800 | [diff] [blame] | 74 | * Environment variable |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 75 | */ |
Chee Hong Ang | f28875c | 2020-12-24 18:20:57 +0800 | [diff] [blame] | 76 | |
| 77 | #ifdef CONFIG_FIT |
| 78 | #define CONFIG_BOOTFILE "kernel.itb" |
Chee Hong Ang | f28875c | 2020-12-24 18:20:57 +0800 | [diff] [blame] | 79 | #else |
| 80 | #define CONFIG_BOOTFILE "Image" |
Chee Hong Ang | f28875c | 2020-12-24 18:20:57 +0800 | [diff] [blame] | 81 | #endif |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 82 | |
| 83 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 84 | "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
Chee Hong Ang | f28875c | 2020-12-24 18:20:57 +0800 | [diff] [blame] | 85 | "bootfile=" CONFIG_BOOTFILE "\0" \ |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 86 | "fdt_addr=8000000\0" \ |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 87 | "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 88 | "mmcroot=/dev/mmcblk0p2\0" \ |
| 89 | "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ |
| 90 | " root=${mmcroot} rw rootwait;" \ |
| 91 | "booti ${loadaddr} - ${fdt_addr}\0" \ |
| 92 | "mmcload=mmc rescan;" \ |
| 93 | "load mmc 0:1 ${loadaddr} ${bootfile};" \ |
| 94 | "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ |
Chee Hong Ang | f28875c | 2020-12-24 18:20:57 +0800 | [diff] [blame] | 95 | "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \ |
| 96 | " root=${mmcroot} rw rootwait;" \ |
| 97 | "bootm ${loadaddr}\0" \ |
| 98 | "mmcfitload=mmc rescan;" \ |
| 99 | "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 100 | "linux_qspi_enable=if sf probe; then " \ |
| 101 | "echo Enabling QSPI at Linux DTB...;" \ |
| 102 | "fdt addr ${fdt_addr}; fdt resize;" \ |
| 103 | "fdt set /soc/spi@ff8d2000 status okay;" \ |
| 104 | "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ |
| 105 | " ${qspi_clock}; fi; \0" \ |
| 106 | "scriptaddr=0x02100000\0" \ |
| 107 | "scriptfile=u-boot.scr\0" \ |
| 108 | "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ |
| 109 | "then source ${scriptaddr}; fi\0" \ |
| 110 | "socfpga_legacy_reset_compat=1\0" |
| 111 | |
| 112 | /* |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 113 | * External memory configurations |
| 114 | */ |
| 115 | #define PHYS_SDRAM_1 0x0 |
| 116 | #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) |
| 117 | #define CONFIG_SYS_SDRAM_BASE 0 |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 118 | |
| 119 | /* |
| 120 | * Serial / UART configurations |
| 121 | */ |
| 122 | #define CONFIG_SYS_NS16550_CLK 100000000 |
| 123 | #define CONFIG_SYS_NS16550_MEM32 |
| 124 | |
| 125 | /* |
| 126 | * Timer & watchdog configurations |
| 127 | */ |
| 128 | #define COUNTER_FREQUENCY 400000000 |
| 129 | |
| 130 | /* |
| 131 | * SDMMC configurations |
| 132 | */ |
| 133 | #ifdef CONFIG_CMD_MMC |
| 134 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 |
| 135 | #endif |
| 136 | /* |
| 137 | * Flash configurations |
| 138 | */ |
| 139 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 140 | |
| 141 | /* Ethernet on SoC (EMAC) */ |
| 142 | #if defined(CONFIG_CMD_NET) |
| 143 | #define CONFIG_DW_ALTDESCRIPTOR |
| 144 | #endif /* CONFIG_CMD_NET */ |
| 145 | |
| 146 | /* |
| 147 | * L4 Watchdog |
| 148 | */ |
Marek Vasut | 8655f67 | 2019-06-27 01:19:23 +0200 | [diff] [blame] | 149 | #ifndef CONFIG_SPL_BUILD |
Marek Vasut | 40919d9 | 2019-06-27 00:26:34 +0200 | [diff] [blame] | 150 | #undef CONFIG_DESIGNWARE_WATCHDOG |
| 151 | #endif |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 152 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 153 | #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 154 | #ifndef __ASSEMBLY__ |
| 155 | unsigned int cm_get_l4_sys_free_clk_hz(void); |
| 156 | #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) |
| 157 | #endif |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 158 | #else |
| 159 | #define CONFIG_DW_WDT_CLOCK_KHZ 100000 |
| 160 | #endif |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 161 | |
| 162 | /* |
| 163 | * SPL memory layout |
| 164 | * |
| 165 | * On chip RAM |
| 166 | * 0xFFE0_0000 ...... Start of OCRAM |
| 167 | * SPL code, rwdata |
| 168 | * empty space |
| 169 | * 0xFFEx_xxxx ...... Top of stack (grows down) |
| 170 | * 0xFFEy_yyyy ...... Global Data |
| 171 | * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) |
| 172 | * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB) |
| 173 | * 0xFFE3_FFFF ...... End of OCRAM |
| 174 | * |
| 175 | * SDRAM |
| 176 | * 0x0000_0000 ...... Start of SDRAM_1 |
| 177 | * unused / empty space for image loading |
| 178 | * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) |
| 179 | * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) |
| 180 | * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) |
| 181 | * |
| 182 | */ |
Dalon Westergreen | 3a8621c | 2021-03-01 20:04:16 +0800 | [diff] [blame] | 183 | #define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 184 | #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE |
| 185 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |
| 186 | #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ |
| 187 | #define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ |
| 188 | - CONFIG_SPL_BSS_MAX_SIZE) |
| 189 | #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) |
| 190 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ |
| 191 | - CONFIG_SYS_SPL_MALLOC_SIZE) |
| 192 | |
| 193 | /* SPL SDMMC boot support */ |
Chee Hong Ang | f28875c | 2020-12-24 18:20:57 +0800 | [diff] [blame] | 194 | #ifdef CONFIG_SPL_LOAD_FIT |
| 195 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" |
| 196 | #else |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 197 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Chee Hong Ang | f28875c | 2020-12-24 18:20:57 +0800 | [diff] [blame] | 198 | #endif |
Ley Foon Tan | c46f6a6 | 2019-11-27 15:55:31 +0800 | [diff] [blame] | 199 | |
| 200 | #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */ |