Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2014 Freescale Semiconductor, Inc. |
Biwen Li | d15aa9f | 2019-12-31 15:33:44 +0800 | [diff] [blame] | 4 | * Copyright 2019 NXP |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __CONFIG_H |
| 8 | #define __CONFIG_H |
| 9 | |
Hongbo Zhang | 912b381 | 2016-07-21 18:09:39 +0800 | [diff] [blame] | 10 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR |
| 11 | |
Tang Yuantian | 8b160bc | 2015-05-14 17:20:28 +0800 | [diff] [blame] | 12 | #define CONFIG_DEEP_SLEEP |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 13 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 14 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR |
| 15 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE |
| 16 | |
York Sun | 1006cad | 2015-04-29 10:35:35 -0700 | [diff] [blame] | 17 | #define DDR_SDRAM_CFG 0x470c0008 |
| 18 | #define DDR_CS0_BNDS 0x008000bf |
| 19 | #define DDR_CS0_CONFIG 0x80014302 |
| 20 | #define DDR_TIMING_CFG_0 0x50550004 |
| 21 | #define DDR_TIMING_CFG_1 0xbcb38c56 |
| 22 | #define DDR_TIMING_CFG_2 0x0040d120 |
| 23 | #define DDR_TIMING_CFG_3 0x010e1000 |
| 24 | #define DDR_TIMING_CFG_4 0x00000001 |
| 25 | #define DDR_TIMING_CFG_5 0x03401400 |
| 26 | #define DDR_SDRAM_CFG_2 0x00401010 |
| 27 | #define DDR_SDRAM_MODE 0x00061c60 |
| 28 | #define DDR_SDRAM_MODE_2 0x00180000 |
| 29 | #define DDR_SDRAM_INTERVAL 0x18600618 |
| 30 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 |
| 31 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 |
| 32 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 |
| 33 | #define DDR_DDR_CDR1 0x80040000 |
| 34 | #define DDR_DDR_CDR2 0x00000001 |
| 35 | #define DDR_SDRAM_CLK_CNTL 0x02000000 |
| 36 | #define DDR_DDR_ZQ_CNTL 0x89080600 |
| 37 | #define DDR_CS0_CONFIG_2 0 |
| 38 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 |
Tang Yuantian | 8b160bc | 2015-05-14 17:20:28 +0800 | [diff] [blame] | 39 | #define SDRAM_CFG2_D_INIT 0x00000010 |
| 40 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 |
| 41 | #define SDRAM_CFG2_FRC_SR 0x80000000 |
| 42 | #define SDRAM_CFG_BI 0x00000001 |
York Sun | 1006cad | 2015-04-29 10:35:35 -0700 | [diff] [blame] | 43 | |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 44 | #ifdef CONFIG_SD_BOOT |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 45 | #ifdef CONFIG_NXP_ESBC |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 46 | /* |
| 47 | * HDR would be appended at end of image and copied to DDR along |
| 48 | * with U-Boot image. |
| 49 | */ |
Semen Protsenko | d776ecf | 2016-11-16 19:19:06 +0200 | [diff] [blame] | 50 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 51 | #endif /* ifdef CONFIG_NXP_ESBC */ |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 52 | |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 53 | #define CONFIG_SPL_MAX_SIZE 0x1a000 |
| 54 | #define CONFIG_SPL_STACK 0x1001d000 |
| 55 | #define CONFIG_SPL_PAD_TO 0x1c000 |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 56 | |
Tang Yuantian | 8b160bc | 2015-05-14 17:20:28 +0800 | [diff] [blame] | 57 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
| 58 | CONFIG_SYS_MONITOR_LEN) |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 59 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 60 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
| 61 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 62 | |
| 63 | #ifdef CONFIG_U_BOOT_HDR_SIZE |
| 64 | /* |
| 65 | * HDR would be appended at end of image and copied to DDR along |
| 66 | * with U-Boot image. Here u-boot max. size is 512K. So if binary |
| 67 | * size increases then increase this size in case of secure boot as |
| 68 | * it uses raw u-boot image instead of fit image. |
| 69 | */ |
Vinitha Pillai | 31b11c6 | 2017-02-01 18:28:53 +0530 | [diff] [blame] | 70 | #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 71 | #else |
Vinitha Pillai | 31b11c6 | 2017-02-01 18:28:53 +0530 | [diff] [blame] | 72 | #define CONFIG_SYS_MONITOR_LEN 0x100000 |
Sumit Garg | e2ca943 | 2016-06-14 13:52:40 -0400 | [diff] [blame] | 73 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 74 | #endif |
| 75 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 76 | #define PHYS_SDRAM 0x80000000 |
| 77 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) |
| 78 | |
| 79 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
| 80 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 81 | |
Alison Wang | d6be97b | 2019-03-06 14:49:14 +0800 | [diff] [blame] | 82 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
| 83 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 84 | /* |
| 85 | * IFC Definitions |
| 86 | */ |
Alison Wang | dd45cc5 | 2015-10-15 17:54:40 +0800 | [diff] [blame] | 87 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 88 | #define CONFIG_SYS_FLASH_BASE 0x60000000 |
| 89 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 90 | |
| 91 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) |
| 92 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| 93 | CSPR_PORT_SIZE_16 | \ |
| 94 | CSPR_MSEL_NOR | \ |
| 95 | CSPR_V) |
| 96 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) |
| 97 | |
| 98 | /* NOR Flash Timing Params */ |
| 99 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 100 | CSOR_NOR_TRHZ_80) |
| 101 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
| 102 | FTIM0_NOR_TEADC(0x5) | \ |
| 103 | FTIM0_NOR_TAVDS(0x0) | \ |
| 104 | FTIM0_NOR_TEAHC(0x5)) |
| 105 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
| 106 | FTIM1_NOR_TRAD_NOR(0x1A) | \ |
| 107 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
| 108 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
| 109 | FTIM2_NOR_TCH(0x4) | \ |
| 110 | FTIM2_NOR_TWP(0x1c) | \ |
| 111 | FTIM2_NOR_TWPH(0x0e)) |
| 112 | #define CONFIG_SYS_NOR_FTIM3 0 |
| 113 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 114 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 115 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 116 | |
| 117 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 118 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 119 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 120 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 121 | |
| 122 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 123 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } |
| 124 | |
| 125 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
Yuan Yao | da17d1a | 2014-10-17 15:26:34 +0800 | [diff] [blame] | 126 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 127 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 128 | |
| 129 | /* CPLD */ |
| 130 | |
| 131 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 |
| 132 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE |
| 133 | |
| 134 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) |
| 135 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ |
| 136 | CSPR_PORT_SIZE_8 | \ |
| 137 | CSPR_MSEL_GPCM | \ |
| 138 | CSPR_V) |
| 139 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) |
| 140 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 141 | CSOR_NOR_NOR_MODE_AVD_NOR | \ |
| 142 | CSOR_NOR_TRHZ_80) |
| 143 | |
| 144 | /* CPLD Timing parameters for IFC GPCM */ |
| 145 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ |
| 146 | FTIM0_GPCM_TEADC(0xf) | \ |
| 147 | FTIM0_GPCM_TEAHC(0xf)) |
| 148 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
| 149 | FTIM1_GPCM_TRAD(0x3f)) |
| 150 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
| 151 | FTIM2_GPCM_TCH(0xf) | \ |
| 152 | FTIM2_GPCM_TWP(0xff)) |
| 153 | #define CONFIG_SYS_FPGA_FTIM3 0x0 |
| 154 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 155 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
| 156 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 157 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 158 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 159 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 160 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 161 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 162 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT |
| 163 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR |
| 164 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK |
| 165 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR |
| 166 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 |
| 167 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 |
| 168 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 |
| 169 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 |
| 170 | |
| 171 | /* |
| 172 | * Serial Port |
| 173 | */ |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 174 | #ifdef CONFIG_LPUART |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 175 | #define CONFIG_LPUART_32B_REG |
| 176 | #else |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 177 | #define CONFIG_SYS_NS16550_SERIAL |
Bin Meng | 06229a9 | 2016-01-13 19:38:59 -0800 | [diff] [blame] | 178 | #ifndef CONFIG_DM_SERIAL |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 179 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
Bin Meng | 06229a9 | 2016-01-13 19:38:59 -0800 | [diff] [blame] | 180 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 181 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 182 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 183 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 184 | /* |
| 185 | * I2C |
| 186 | */ |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 187 | |
Biwen Li | e5bd713 | 2021-02-05 19:02:02 +0800 | [diff] [blame] | 188 | /* GPIO */ |
Biwen Li | e5bd713 | 2021-02-05 19:02:02 +0800 | [diff] [blame] | 189 | |
Alison Wang | af276f4 | 2014-10-17 15:26:35 +0800 | [diff] [blame] | 190 | /* EEPROM */ |
Alison Wang | af276f4 | 2014-10-17 15:26:35 +0800 | [diff] [blame] | 191 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 192 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
Alison Wang | af276f4 | 2014-10-17 15:26:35 +0800 | [diff] [blame] | 193 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 194 | /* |
| 195 | * MMC |
| 196 | */ |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 197 | |
| 198 | /* |
Wang Huan | 9207219 | 2014-09-05 13:52:50 +0800 | [diff] [blame] | 199 | * Video |
| 200 | */ |
Sanchayan Maity | e15479b | 2017-04-11 11:12:09 +0530 | [diff] [blame] | 201 | #ifdef CONFIG_VIDEO_FSL_DCU_FB |
Wang Huan | 9207219 | 2014-09-05 13:52:50 +0800 | [diff] [blame] | 202 | #define CONFIG_VIDEO_BMP_LOGO |
| 203 | |
| 204 | #define CONFIG_FSL_DCU_SII9022A |
| 205 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 |
| 206 | #define CONFIG_SYS_I2C_DVI_ADDR 0x39 |
| 207 | #endif |
| 208 | |
| 209 | /* |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 210 | * eTSEC |
| 211 | */ |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 212 | |
| 213 | #ifdef CONFIG_TSEC_ENET |
Bin Meng | 19c0460 | 2019-07-19 00:29:59 +0300 | [diff] [blame] | 214 | #define CONFIG_ETHPRIME "ethernet@2d10000" |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 215 | #endif |
| 216 | |
Minghuan Lian | a4d6b61 | 2014-10-31 13:43:44 +0800 | [diff] [blame] | 217 | /* PCIe */ |
Robert P. J. Day | a809981 | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 218 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 219 | #define CONFIG_PCIE2 /* PCIE controller 2 */ |
Minghuan Lian | a4d6b61 | 2014-10-31 13:43:44 +0800 | [diff] [blame] | 220 | |
Minghuan Lian | 0c1593a | 2015-01-21 17:29:19 +0800 | [diff] [blame] | 221 | #ifdef CONFIG_PCI |
Minghuan Lian | 0c1593a | 2015-01-21 17:29:19 +0800 | [diff] [blame] | 222 | #define CONFIG_PCI_SCAN_SHOW |
Minghuan Lian | 0c1593a | 2015-01-21 17:29:19 +0800 | [diff] [blame] | 223 | #endif |
| 224 | |
Xiubo Li | 563e3ce | 2014-11-21 17:40:57 +0800 | [diff] [blame] | 225 | #define CONFIG_PEN_ADDR_BIG_ENDIAN |
Mingkai Hu | 5b0df8a | 2015-10-26 19:47:41 +0800 | [diff] [blame] | 226 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
Xiubo Li | 563e3ce | 2014-11-21 17:40:57 +0800 | [diff] [blame] | 227 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
Andre Przywara | 70c7893 | 2017-02-16 01:20:19 +0000 | [diff] [blame] | 228 | #define COUNTER_FREQUENCY 12500000 |
Xiubo Li | 563e3ce | 2014-11-21 17:40:57 +0800 | [diff] [blame] | 229 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 230 | #define CONFIG_HWCONFIG |
Zhuoyu Zhang | fe4f288 | 2015-08-17 18:55:12 +0800 | [diff] [blame] | 231 | #define HWCONFIG_BUFFER_SIZE 256 |
| 232 | |
| 233 | #define CONFIG_FSL_DEVICE_DISABLE |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 234 | |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 235 | #define BOOT_TARGET_DEVICES(func) \ |
| 236 | func(MMC, mmc, 0) \ |
Yunfeng Ding | 0c1d95e | 2019-02-19 14:44:04 +0800 | [diff] [blame] | 237 | func(USB, usb, 0) \ |
| 238 | func(DHCP, dhcp, na) |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 239 | #include <config_distro_bootcmd.h> |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 240 | |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 241 | #ifdef CONFIG_LPUART |
| 242 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Alison Wang | 6a8e978 | 2020-04-23 22:37:34 +0800 | [diff] [blame] | 243 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \ |
| 244 | "cma=64M@0x0-0xb0000000\0" \ |
Alison Wang | ec2ab3c | 2015-10-26 14:08:28 +0800 | [diff] [blame] | 245 | "initrd_high=0xffffffff\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 246 | "fdt_addr=0x64f00000\0" \ |
| 247 | "kernel_addr=0x65000000\0" \ |
| 248 | "scriptaddr=0x80000000\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 249 | "scripthdraddr=0x80080000\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 250 | "fdtheader_addr_r=0x80100000\0" \ |
| 251 | "kernelheader_addr_r=0x80200000\0" \ |
| 252 | "kernel_addr_r=0x81000000\0" \ |
| 253 | "fdt_addr_r=0x90000000\0" \ |
| 254 | "ramdisk_addr_r=0xa0000000\0" \ |
| 255 | "load_addr=0xa0000000\0" \ |
| 256 | "kernel_size=0x2800000\0" \ |
Shengzhou Liu | 7c8dbe2 | 2017-11-09 17:57:57 +0800 | [diff] [blame] | 257 | "kernel_addr_sd=0x8000\0" \ |
| 258 | "kernel_size_sd=0x14000\0" \ |
Alison Wang | d168ade | 2020-01-21 07:33:01 +0000 | [diff] [blame] | 259 | "othbootargs=cma=64M@0x0-0xb0000000\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 260 | BOOTENV \ |
| 261 | "boot_scripts=ls1021atwr_boot.scr\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 262 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 263 | "scan_dev_for_boot_part=" \ |
| 264 | "part list ${devtype} ${devnum} devplist; " \ |
| 265 | "env exists devplist || setenv devplist 1; " \ |
| 266 | "for distro_bootpart in ${devplist}; do " \ |
| 267 | "if fstype ${devtype} " \ |
| 268 | "${devnum}:${distro_bootpart} " \ |
| 269 | "bootfstype; then " \ |
| 270 | "run scan_dev_for_boot; " \ |
| 271 | "fi; " \ |
| 272 | "done\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 273 | "scan_dev_for_boot=" \ |
| 274 | "echo Scanning ${devtype} " \ |
| 275 | "${devnum}:${distro_bootpart}...; " \ |
| 276 | "for prefix in ${boot_prefixes}; do " \ |
| 277 | "run scan_dev_for_scripts; " \ |
| 278 | "done;" \ |
| 279 | "\0" \ |
| 280 | "boot_a_script=" \ |
| 281 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 282 | "${scriptaddr} ${prefix}${script}; " \ |
| 283 | "env exists secureboot && load ${devtype} " \ |
| 284 | "${devnum}:${distro_bootpart} " \ |
Vinitha V Pillai | 25355ec | 2019-04-23 05:52:17 +0000 | [diff] [blame] | 285 | "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ |
| 286 | "env exists secureboot " \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 287 | "&& esbc_validate ${scripthdraddr};" \ |
| 288 | "source ${scriptaddr}\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 289 | "installer=load mmc 0:2 $load_addr " \ |
| 290 | "/flex_installer_arm32.itb; " \ |
| 291 | "bootm $load_addr#ls1021atwr\0" \ |
| 292 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
| 293 | "sf probe && sf read $load_addr " \ |
| 294 | "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ |
| 295 | "nor_bootcmd=echo Trying load from nor..;" \ |
| 296 | "cp.b $kernel_addr $load_addr " \ |
| 297 | "$kernel_size && bootm $load_addr#$board\0" |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 298 | #else |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 299 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Alison Wang | 6a8e978 | 2020-04-23 22:37:34 +0800 | [diff] [blame] | 300 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \ |
| 301 | "cma=64M@0x0-0xb0000000\0" \ |
Alison Wang | ec2ab3c | 2015-10-26 14:08:28 +0800 | [diff] [blame] | 302 | "initrd_high=0xffffffff\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 303 | "fdt_addr=0x64f00000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 304 | "kernel_addr=0x61000000\0" \ |
| 305 | "kernelheader_addr=0x60800000\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 306 | "scriptaddr=0x80000000\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 307 | "scripthdraddr=0x80080000\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 308 | "fdtheader_addr_r=0x80100000\0" \ |
| 309 | "kernelheader_addr_r=0x80200000\0" \ |
| 310 | "kernel_addr_r=0x81000000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 311 | "kernelheader_size=0x40000\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 312 | "fdt_addr_r=0x90000000\0" \ |
| 313 | "ramdisk_addr_r=0xa0000000\0" \ |
| 314 | "load_addr=0xa0000000\0" \ |
| 315 | "kernel_size=0x2800000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 316 | "kernel_addr_sd=0x8000\0" \ |
| 317 | "kernel_size_sd=0x14000\0" \ |
| 318 | "kernelhdr_addr_sd=0x4000\0" \ |
| 319 | "kernelhdr_size_sd=0x10\0" \ |
Alison Wang | d168ade | 2020-01-21 07:33:01 +0000 | [diff] [blame] | 320 | "othbootargs=cma=64M@0x0-0xb0000000\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 321 | BOOTENV \ |
| 322 | "boot_scripts=ls1021atwr_boot.scr\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 323 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 324 | "scan_dev_for_boot_part=" \ |
| 325 | "part list ${devtype} ${devnum} devplist; " \ |
| 326 | "env exists devplist || setenv devplist 1; " \ |
| 327 | "for distro_bootpart in ${devplist}; do " \ |
| 328 | "if fstype ${devtype} " \ |
| 329 | "${devnum}:${distro_bootpart} " \ |
| 330 | "bootfstype; then " \ |
| 331 | "run scan_dev_for_boot; " \ |
| 332 | "fi; " \ |
| 333 | "done\0" \ |
Sumit Garg | 50f1467 | 2017-06-06 20:51:31 +0530 | [diff] [blame] | 334 | "scan_dev_for_boot=" \ |
| 335 | "echo Scanning ${devtype} " \ |
| 336 | "${devnum}:${distro_bootpart}...; " \ |
| 337 | "for prefix in ${boot_prefixes}; do " \ |
| 338 | "run scan_dev_for_scripts; " \ |
| 339 | "done;" \ |
| 340 | "\0" \ |
| 341 | "boot_a_script=" \ |
| 342 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 343 | "${scriptaddr} ${prefix}${script}; " \ |
| 344 | "env exists secureboot && load ${devtype} " \ |
| 345 | "${devnum}:${distro_bootpart} " \ |
| 346 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ |
| 347 | "&& esbc_validate ${scripthdraddr};" \ |
| 348 | "source ${scriptaddr}\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 349 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
| 350 | "sf probe && sf read $load_addr " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 351 | "$kernel_addr $kernel_size; env exists secureboot " \ |
| 352 | "&& sf read $kernelheader_addr_r $kernelheader_addr " \ |
| 353 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 354 | "bootm $load_addr#$board\0" \ |
Alison Wang | a999c9d | 2017-05-26 15:46:15 +0800 | [diff] [blame] | 355 | "nor_bootcmd=echo Trying load from nor..;" \ |
| 356 | "cp.b $kernel_addr $load_addr " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 357 | "$kernel_size; env exists secureboot " \ |
| 358 | "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ |
| 359 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 360 | "bootm $load_addr#$board\0" \ |
Shengzhou Liu | 7c8dbe2 | 2017-11-09 17:57:57 +0800 | [diff] [blame] | 361 | "sd_bootcmd=echo Trying load from SD ..;" \ |
| 362 | "mmcinfo && mmc read $load_addr " \ |
| 363 | "$kernel_addr_sd $kernel_size_sd && " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 364 | "env exists secureboot && mmc read $kernelheader_addr_r " \ |
| 365 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ |
| 366 | " && esbc_validate ${kernelheader_addr_r};" \ |
Shengzhou Liu | 7c8dbe2 | 2017-11-09 17:57:57 +0800 | [diff] [blame] | 367 | "bootm $load_addr#$board\0" |
Alison Wang | 2a397ce | 2015-01-04 15:30:59 +0800 | [diff] [blame] | 368 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 369 | |
| 370 | /* |
| 371 | * Miscellaneous configurable options |
| 372 | */ |
Alison Wang | 7147706 | 2020-02-03 15:25:19 +0800 | [diff] [blame] | 373 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 374 | |
Xiubo Li | 03d40aa | 2014-11-21 17:40:59 +0800 | [diff] [blame] | 375 | #define CONFIG_LS102XA_STREAM_ID |
| 376 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 377 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 378 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 379 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 380 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 381 | |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 382 | #ifdef CONFIG_SPL_BUILD |
| 383 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 384 | #else |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 385 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Alison Wang | 948c609 | 2014-12-03 15:00:48 +0800 | [diff] [blame] | 386 | #endif |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 387 | |
| 388 | /* |
| 389 | * Environment |
| 390 | */ |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 391 | |
Aneesh Bansal | 962021a | 2016-01-22 16:37:22 +0530 | [diff] [blame] | 392 | #include <asm/fsl_secure_boot.h> |
Alison Wang | 13b0bb8 | 2016-01-15 15:29:32 +0800 | [diff] [blame] | 393 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Ruchika Gupta | 901ae76 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 394 | |
Wang Huan | ddf89f9 | 2014-09-05 13:52:45 +0800 | [diff] [blame] | 395 | #endif |