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git01.mediatek.com / filogic / uboot / 1ef91feb56a849f1ac19a7c5460b20fdd1f43c83 / . / arch / riscv / dts / ae350.dts
blob: 4717ae88bc0849efc316e11b9921acec16ef5933 [file] [log] [blame]
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]1/dts-v1/;
Rick Chenc7cccef2018-05-29 10:53:41 +0800[diff] [blame]2
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]3/ {
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]4 #address-cells = <2>;
5 #size-cells = <2>;
6 compatible = "andestech,ax25";
7 model = "andestech,ax25";
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]8
9 aliases {
10 uart0 = &serial0;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]11 spi0 = &spi;
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]12 };
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]13
14 chosen {
15 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
16 stdout-path = "uart0:38400n8";
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]17 };
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22 timebase-frequency = <10000000>;
23
24 CPU0: cpu@0 {
25 device_type = "cpu";
26 reg = <0>;
27 status = "okay";
28 compatible = "riscv";
29 riscv,isa = "rv64imafdc";
30 mmu-type = "riscv,sv39";
31 clock-frequency = <60000000>;
Rick Chenc7cccef2018-05-29 10:53:41 +0800[diff] [blame]32
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]33 CPU0_intc: interrupt-controller {
34 #interrupt-cells = <1>;
35 interrupt-controller;
36 compatible = "riscv,cpu-intc";
37 };
38 };
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]39 };
40
41 memory@0 {
42 device_type = "memory";
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]43 reg = <0x0 0x00000000 0x0 0x40000000>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]44 };
45
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]46 soc {
47 #address-cells = <2>;
48 #size-cells = <2>;
49 compatible = "andestech,riscv-ae350-soc";
50 ranges;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]51 };
52
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]53 plmt0@e6000000 {
54 compatible = "riscv,plmt0";
55 interrupts-extended = <&CPU0_intc 7>;
56 reg = <0x0 0xe6000000 0x0 0x100000>;
57 };
Rick Chenc7cccef2018-05-29 10:53:41 +0800[diff] [blame]58
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]59 plic0: interrupt-controller@e4000000 {
60 compatible = "riscv,plic0";
61 #address-cells = <2>;
62 #interrupt-cells = <2>;
63 interrupt-controller;
64 reg = <0x0 0xe4000000 0x0 0x2000000>;
65 riscv,ndev=<31>;
66 interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]67 };
68
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]69 plic1: interrupt-controller@e6400000 {
70 compatible = "riscv,plic1";
71 #address-cells = <2>;
72 #interrupt-cells = <2>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]73 interrupt-controller;
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]74 reg = <0x0 0xe6400000 0x0 0x400000>;
75 riscv,ndev=<1>;
76 interrupts-extended = <&CPU0_intc 3>;
77 };
Rick Chenc7cccef2018-05-29 10:53:41 +0800[diff] [blame]78
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]79 spiclk: virt_100mhz {
80 #clock-cells = <0>;
81 compatible = "fixed-clock";
82 clock-frequency = <100000000>;
83 };
Rick Chenc7cccef2018-05-29 10:53:41 +0800[diff] [blame]84
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]85 timer0: timer@f0400000 {
86 compatible = "andestech,atcpit100";
87 reg = <0x0 0xf0400000 0x0 0x1000>;
88 clock-frequency = <40000000>;
89 interrupts = <3 4>;
90 interrupt-parent = <&plic0>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]91 };
92
93 serial0: serial@f0300000 {
94 compatible = "andestech,uart16550", "ns16550a";
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]95 reg = <0x0 0xf0300000 0x0 0x1000>;
96 interrupts = <9 4>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]97 clock-frequency = <19660800>;
98 reg-shift = <2>;
99 reg-offset = <32>;
100 no-loopback-test = <1>;
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]101 interrupt-parent = <&plic0>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]102 };
103
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]104 mac0: mac@e0100000 {
105 compatible = "andestech,atmac100";
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]106 reg = <0x0 0xe0100000 0x0 0x1000>;
107 interrupts = <19 4>;
108 interrupt-parent = <&plic0>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]109 };
110
111 mmc0: mmc@f0e00000 {
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]112 compatible = "andestech,atfsdc010";
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]113 max-frequency = <100000000>;
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]114 clock-freq-min-max = <400000 100000000>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]115 fifo-depth = <0x10>;
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]116 reg = <0x0 0xf0e00000 0x0 0x1000>;
117 interrupts = <18 4>;
Rick Chenef6b1962017-12-25 17:05:39 +0800[diff] [blame]118 cap-sd-highspeed;
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]119 interrupt-parent = <&plic0>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]120 };
121
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]122 smc0: smc@e0400000 {
123 compatible = "andestech,atfsmc020";
124 reg = <0x0 0xe0400000 0x0 0x1000>;
125 };
Rick Chened4a3b32018-05-29 11:05:54 +0800[diff] [blame]126
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]127 nor@0,0 {
128 compatible = "cfi-flash";
129 reg = <0x0 0x88000000 0x0 0x1000>;
130 bank-width = <2>;
131 device-width = <1>;
132 };
Rick Chened4a3b32018-05-29 11:05:54 +0800[diff] [blame]133
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]134 spi: spi@f0b00000 {
135 compatible = "andestech,atcspi200";
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]136 reg = <0x0 0xf0b00000 0x0 0x1000>;
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]137 #address-cells = <1>;
138 #size-cells = <0>;
139 num-cs = <1>;
140 clocks = <&spiclk>;
141 interrupts = <3 4>;
Bin Meng6e1033f2018-09-26 06:55:18 -0700[diff] [blame]142 interrupt-parent = <&plic0>;
143
144 flash@0 {
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]145 compatible = "spi-flash";
146 spi-max-frequency = <50000000>;
147 reg = <0>;
148 spi-cpol;
149 spi-cpha;
150 };
151 };
Rick Chen2e4fc1b2017-12-26 13:55:50 +0800[diff] [blame]152};