| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 1 | The port was tested on Wind River System Sbc8560 board |
| 2 | <www.windriver.com>. U-Boot was installed on the flash memory of the |
| 3 | CPU card (no the SODIMM). |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 4 | |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 5 | NOTE: Please configure uboot compile to the proper PCI frequency and |
| 6 | setup the appropriate DIP switch settings. |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 7 | |
| 8 | SBC8560 board: |
| 9 | |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 10 | Make sure boards switches are set to their appropriate conditions. |
| 11 | Refer to the Engineering Reference Guide ERG-00300-002. Of particular |
| 12 | importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which |
| 13 | select the on-board FLASH device (Intel 28F128Jx); 2) The settings |
| 14 | for the Clock SW9 (33 MHz or 66 MHz). |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 15 | |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 16 | Note: SW9 Settings: 66 MHz |
| 17 | 4:1 ratio CCB clocks:SYSCLK |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 18 | 3:1 ration e500 Core:CCB |
| 19 | pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 20 | Note: SW9 Settings: 33 MHz |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 21 | 8:1 ratio CCB clocks:SYSCLK |
| 22 | 3:1 ration e500 Core:CCB |
| 23 | pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 24 | |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 25 | |
| 26 | Flashing the FLASH device with the "Wind River ICE": |
| 27 | |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 28 | 1) Properly connect and configure the Wind River ICE to the target |
| 29 | JTAG port. This includes running the SBC8560 register script. Make |
| 30 | sure target memory can be read and written. |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 31 | |
| 32 | 2) Build the u-boot image: |
| 33 | make distclean |
| 34 | make SBC8560_66_config or SBC8560_33_config |
| 35 | make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all |
| 36 | |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 37 | Note: reference is made to the ELDK3.0 compiler. Further, it seems |
| 38 | the ppc_8xx compiler is required for the 85xx (no 85xx |
| 39 | designated compiler in ELDK3.0) |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 40 | |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 41 | 3) Convert the uboot (.elf) file to a uboot.bin file (using |
| 42 | visionClick converter). The bin file should be converted from |
| 43 | fffc0000 to ffffffff |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 44 | |
| 45 | 4) Setup the Flash Utility (tools menu) for: |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 46 | |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 47 | Do a "dc clr" [visionClick] to load the default register settings |
| 48 | Determine the clock speed of the PCI bus and set SW9 accordingly |
| wdenk | 17b211b | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 49 | Note: the speed of the PCI bus defaults to the slowest PCI card |
| wdenk | adf849c | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 50 | PlayBack the "default" register file for the SBC8560 |
| 51 | Select the uboot.bin file with zero bias |
| 52 | Select the initialize Target prior to programming |
| 53 | Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm |
| 54 | Select the erase base address from FFFC0000 to FFFFFFFF |
| 55 | Select the start address from 0 with size of 4000 |
| 56 | |
| 57 | 5) Erase and Program |