blob: f0cc34d788e196a33a6092099d19335323b8db0a [file] [log] [blame]
Shengzhou Liu11ff48a2014-04-18 16:43:40 +08001/* Copyright 2013 Freescale Semiconductor, Inc.
2 *
3 * SPDX-License-Identifier: GPL-2.0+
4 */
5
6#include <common.h>
Simon Glassa73bda42015-11-08 23:47:45 -07007#include <console.h>
Simon Glass4bc2ad22017-08-03 12:21:56 -06008#include <environment.h>
Shengzhou Liu11ff48a2014-04-18 16:43:40 +08009#include <malloc.h>
10#include <ns16550.h>
11#include <nand.h>
12#include <i2c.h>
13#include <mmc.h>
14#include <fsl_esdhc.h>
15#include <spi_flash.h>
Simon Glassdd8e2242016-09-24 18:20:10 -060016#include "../common/spl.h"
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080017
18DECLARE_GLOBAL_DATA_PTR;
19
20phys_size_t get_effective_memsize(void)
21{
22 return CONFIG_SYS_L3_SIZE;
23}
24
25unsigned long get_board_sys_clk(void)
26{
27 return CONFIG_SYS_CLK_FREQ;
28}
29
30unsigned long get_board_ddr_clk(void)
31{
32 return CONFIG_DDR_CLK_FREQ;
33}
34
35void board_init_f(ulong bootflag)
36{
37 u32 plat_ratio, sys_clk, ccb_clk;
38 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
39
40 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
41 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
42
43 /* Update GD pointer */
44 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
45
46 console_init_f();
47
48 /* initialize selected port with appropriate baud rate */
49 sys_clk = get_board_sys_clk();
50 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
51 ccb_clk = sys_clk * plat_ratio / 2;
52
53 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
54 ccb_clk / 16 / CONFIG_BAUDRATE);
55
56#if defined(CONFIG_SPL_MMC_BOOT)
57 puts("\nSD boot...\n");
58#elif defined(CONFIG_SPL_SPI_BOOT)
59 puts("\nSPI boot...\n");
60#elif defined(CONFIG_SPL_NAND_BOOT)
61 puts("\nNAND boot...\n");
62#endif
63
64 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
65}
66
67void board_init_r(gd_t *gd, ulong dest_addr)
68{
69 bd_t *bd;
70
71 bd = (bd_t *)(gd + sizeof(gd_t));
72 memset(bd, 0, sizeof(bd_t));
73 gd->bd = bd;
74 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
75 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
76
Simon Glass302445a2017-01-23 13:31:22 -070077 arch_cpu_init();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080078 get_clocks();
79 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
80 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -040081 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080082
83#ifdef CONFIG_SPL_NAND_BOOT
84 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
85 (uchar *)CONFIG_ENV_ADDR);
86#endif
87#ifdef CONFIG_SPL_MMC_BOOT
88 mmc_initialize(bd);
89 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
90 (uchar *)CONFIG_ENV_ADDR);
91#endif
92#ifdef CONFIG_SPL_SPI_BOOT
Simon Glassdd8e2242016-09-24 18:20:10 -060093 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
94 (uchar *)CONFIG_ENV_ADDR);
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080095#endif
96
97 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -060098 gd->env_valid = ENV_VALID;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080099
100 i2c_init_all();
101
Simon Glassd35f3382017-04-06 12:47:05 -0600102 dram_init();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +0800103
104#ifdef CONFIG_SPL_MMC_BOOT
105 mmc_boot();
106#elif defined(CONFIG_SPL_SPI_BOOT)
Simon Glassdd8e2242016-09-24 18:20:10 -0600107 fsl_spi_boot();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +0800108#elif defined(CONFIG_SPL_NAND_BOOT)
109 nand_boot();
110#endif
111}