blob: 3c9eb1431677e8c3c258bb58b0cd73617eaee018 [file] [log] [blame]
Jagan Tekie366a0c2019-01-11 15:41:46 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -050011#include <clk/sunxi.h>
Jagan Tekie366a0c2019-01-11 15:41:46 +053012#include <dt-bindings/clock/sun9i-a80-ccu.h>
13#include <dt-bindings/reset/sun9i-a80-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Jagan Tekie366a0c2019-01-11 15:41:46 +053015
16static const struct ccu_clk_gate a80_gates[] = {
Jagan Tekibc123132019-02-27 20:02:06 +053017 [CLK_SPI0] = GATE(0x430, BIT(31)),
18 [CLK_SPI1] = GATE(0x434, BIT(31)),
19 [CLK_SPI2] = GATE(0x438, BIT(31)),
20 [CLK_SPI3] = GATE(0x43c, BIT(31)),
21
Andre Przywaraddf33c12019-01-29 15:54:09 +000022 [CLK_BUS_MMC] = GATE(0x580, BIT(8)),
Jagan Tekibc123132019-02-27 20:02:06 +053023 [CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
24 [CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
25 [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
26 [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
Andre Przywaraddf33c12019-01-29 15:54:09 +000027
Andre Przywara3e9aa0b2022-05-04 22:10:28 +010028 [CLK_BUS_PIO] = GATE(0x590, BIT(5)),
29
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050030 [CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
31 [CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
32 [CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
33 [CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
34 [CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
Jagan Tekie366a0c2019-01-11 15:41:46 +053035 [CLK_BUS_UART0] = GATE(0x594, BIT(16)),
36 [CLK_BUS_UART1] = GATE(0x594, BIT(17)),
37 [CLK_BUS_UART2] = GATE(0x594, BIT(18)),
38 [CLK_BUS_UART3] = GATE(0x594, BIT(19)),
39 [CLK_BUS_UART4] = GATE(0x594, BIT(20)),
40 [CLK_BUS_UART5] = GATE(0x594, BIT(21)),
41};
42
43static const struct ccu_reset a80_resets[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +000044 [RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
Jagan Tekibc123132019-02-27 20:02:06 +053045 [RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
46 [RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
47 [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
48 [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
Andre Przywaraddf33c12019-01-29 15:54:09 +000049
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050050 [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
51 [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
52 [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
53 [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
54 [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
Jagan Tekie366a0c2019-01-11 15:41:46 +053055 [RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
56 [RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
57 [RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
58 [RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
59 [RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
60 [RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
61};
62
Andre Przywara8c8c8a42019-01-29 15:54:10 +000063static const struct ccu_clk_gate a80_mmc_gates[] = {
64 [0] = GATE(0x0, BIT(16)),
65 [1] = GATE(0x4, BIT(16)),
66 [2] = GATE(0x8, BIT(16)),
67 [3] = GATE(0xc, BIT(16)),
68};
69
70static const struct ccu_reset a80_mmc_resets[] = {
71 [0] = GATE(0x0, BIT(18)),
72 [1] = GATE(0x4, BIT(18)),
73 [2] = GATE(0x8, BIT(18)),
74 [3] = GATE(0xc, BIT(18)),
75};
76
Samuel Holland751c6c62022-05-09 00:29:34 -050077const struct ccu_desc a80_ccu_desc = {
Jagan Tekie366a0c2019-01-11 15:41:46 +053078 .gates = a80_gates,
79 .resets = a80_resets,
Samuel Holland84436502022-05-09 00:29:31 -050080 .num_gates = ARRAY_SIZE(a80_gates),
81 .num_resets = ARRAY_SIZE(a80_resets),
Jagan Tekie366a0c2019-01-11 15:41:46 +053082};
83
Samuel Holland751c6c62022-05-09 00:29:34 -050084const struct ccu_desc a80_mmc_clk_desc = {
Andre Przywara8c8c8a42019-01-29 15:54:10 +000085 .gates = a80_mmc_gates,
86 .resets = a80_mmc_resets,
Samuel Holland84436502022-05-09 00:29:31 -050087 .num_gates = ARRAY_SIZE(a80_mmc_gates),
88 .num_resets = ARRAY_SIZE(a80_mmc_resets),
Andre Przywara8c8c8a42019-01-29 15:54:10 +000089};