David Huang | 6109820 | 2022-01-25 20:56:31 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * J721E: SoC specific initialization |
| 4 | * |
| 5 | * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ |
| 6 | * David Huang <d-huang@ti.com> |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <init.h> |
| 11 | #include <spl.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <asm/armv7_mpu.h> |
| 14 | #include <asm/arch/hardware.h> |
| 15 | #include <asm/arch/sysfw-loader.h> |
| 16 | #include "common.h" |
| 17 | #include <asm/arch/sys_proto.h> |
| 18 | #include <linux/soc/ti/ti_sci_protocol.h> |
| 19 | #include <dm.h> |
| 20 | #include <dm/uclass-internal.h> |
| 21 | #include <dm/pinctrl.h> |
| 22 | #include <mmc.h> |
| 23 | #include <remoteproc.h> |
| 24 | |
| 25 | #ifdef CONFIG_SPL_BUILD |
| 26 | |
| 27 | static void ctrl_mmr_unlock(void) |
| 28 | { |
| 29 | /* Unlock all WKUP_CTRL_MMR0 module registers */ |
| 30 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); |
| 31 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); |
| 32 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); |
| 33 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); |
| 34 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); |
| 35 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); |
| 36 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); |
| 37 | |
| 38 | /* Unlock all MCU_CTRL_MMR0 module registers */ |
| 39 | mmr_unlock(MCU_CTRL_MMR0_BASE, 0); |
| 40 | mmr_unlock(MCU_CTRL_MMR0_BASE, 1); |
| 41 | mmr_unlock(MCU_CTRL_MMR0_BASE, 2); |
| 42 | mmr_unlock(MCU_CTRL_MMR0_BASE, 3); |
| 43 | mmr_unlock(MCU_CTRL_MMR0_BASE, 4); |
| 44 | |
| 45 | /* Unlock all CTRL_MMR0 module registers */ |
| 46 | mmr_unlock(CTRL_MMR0_BASE, 0); |
| 47 | mmr_unlock(CTRL_MMR0_BASE, 1); |
| 48 | mmr_unlock(CTRL_MMR0_BASE, 2); |
| 49 | mmr_unlock(CTRL_MMR0_BASE, 3); |
| 50 | mmr_unlock(CTRL_MMR0_BASE, 5); |
| 51 | mmr_unlock(CTRL_MMR0_BASE, 7); |
| 52 | } |
| 53 | |
| 54 | void k3_mmc_stop_clock(void) |
| 55 | { |
| 56 | if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) { |
| 57 | if (spl_boot_device() == BOOT_DEVICE_MMC1) { |
| 58 | struct mmc *mmc = find_mmc_device(0); |
| 59 | |
| 60 | if (!mmc) |
| 61 | return; |
| 62 | |
| 63 | mmc->saved_clock = mmc->clock; |
| 64 | mmc_set_clock(mmc, 0, true); |
| 65 | } |
| 66 | } |
| 67 | } |
| 68 | |
| 69 | void k3_mmc_restart_clock(void) |
| 70 | { |
| 71 | if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) { |
| 72 | if (spl_boot_device() == BOOT_DEVICE_MMC1) { |
| 73 | struct mmc *mmc = find_mmc_device(0); |
| 74 | |
| 75 | if (!mmc) |
| 76 | return; |
| 77 | |
| 78 | mmc_set_clock(mmc, mmc->saved_clock, false); |
| 79 | } |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | /* |
| 84 | * This uninitialized global variable would normal end up in the .bss section, |
| 85 | * but the .bss is cleared between writing and reading this variable, so move |
| 86 | * it to the .data section. |
| 87 | */ |
| 88 | u32 bootindex __attribute__((section(".data"))); |
| 89 | static struct rom_extended_boot_data bootdata __section(".data"); |
| 90 | |
| 91 | static void store_boot_info_from_rom(void) |
| 92 | { |
| 93 | bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); |
| 94 | memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, |
| 95 | sizeof(struct rom_extended_boot_data)); |
| 96 | } |
| 97 | |
| 98 | void board_init_f(ulong dummy) |
| 99 | { |
| 100 | struct udevice *dev; |
| 101 | int ret; |
| 102 | /* |
| 103 | * Cannot delay this further as there is a chance that |
| 104 | * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. |
| 105 | */ |
| 106 | store_boot_info_from_rom(); |
| 107 | |
| 108 | /* Make all control module registers accessible */ |
| 109 | ctrl_mmr_unlock(); |
| 110 | |
| 111 | if (IS_ENABLED(CONFIG_CPU_V7R)) { |
| 112 | disable_linefill_optimization(); |
| 113 | setup_k3_mpu_regions(); |
| 114 | } |
| 115 | |
| 116 | /* Init DM early */ |
| 117 | spl_early_init(); |
| 118 | |
| 119 | /* Prepare console output */ |
| 120 | preloader_console_init(); |
| 121 | |
| 122 | if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) { |
| 123 | /* |
| 124 | * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue |
| 125 | * regardless of the result of pinctrl. Do this without probing the |
| 126 | * device, but instead by searching the device that would request the |
| 127 | * given sequence number if probed. The UART will be used by the system |
| 128 | * firmware (SYSFW) image for various purposes and SYSFW depends on us |
| 129 | * to initialize its pin settings. |
| 130 | */ |
| 131 | ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); |
| 132 | if (!ret) |
| 133 | pinctrl_select_state(dev, "default"); |
| 134 | |
| 135 | /* |
| 136 | * Load, start up, and configure system controller firmware. Provide |
| 137 | * the U-Boot console init function to the SYSFW post-PM configuration |
| 138 | * callback hook, effectively switching on (or over) the console |
| 139 | * output. |
| 140 | */ |
| 141 | k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), |
| 142 | k3_mmc_stop_clock, k3_mmc_restart_clock); |
| 143 | |
| 144 | if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { |
| 145 | /* |
| 146 | * Force probe of clk_k3 driver here to ensure basic default clock |
| 147 | * configuration is always done for enabling PM services. |
| 148 | */ |
| 149 | ret = uclass_get_device_by_driver(UCLASS_CLK, |
| 150 | DM_DRIVER_GET(ti_clk), |
| 151 | &dev); |
| 152 | if (ret) |
| 153 | panic("Failed to initialize clk-k3!\n"); |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | /* Output System Firmware version info */ |
| 158 | k3_sysfw_print_ver(); |
| 159 | |
| 160 | if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) { |
| 161 | ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev); |
| 162 | if (ret) |
| 163 | panic("Probe of msmc failed: %d\n", ret); |
| 164 | |
| 165 | ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
| 166 | if (ret) |
| 167 | panic("DRAM 0 init failed: %d\n", ret); |
| 168 | |
| 169 | ret = uclass_next_device(&dev); |
| 170 | if (ret) |
| 171 | panic("DRAM 1 init failed: %d\n", ret); |
| 172 | } |
| 173 | spl_enable_dcache(); |
| 174 | } |
| 175 | |
Andre Przywara | 3cb12ef | 2021-07-12 11:06:49 +0100 | [diff] [blame] | 176 | u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) |
David Huang | 6109820 | 2022-01-25 20:56:31 +0530 | [diff] [blame] | 177 | { |
| 178 | switch (boot_device) { |
| 179 | case BOOT_DEVICE_MMC1: |
| 180 | return MMCSD_MODE_EMMCBOOT; |
| 181 | case BOOT_DEVICE_MMC2: |
| 182 | return MMCSD_MODE_FS; |
| 183 | default: |
| 184 | return MMCSD_MODE_RAW; |
| 185 | } |
| 186 | } |
| 187 | |
| 188 | static u32 __get_backup_bootmedia(u32 main_devstat) |
| 189 | { |
| 190 | u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >> |
| 191 | MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT; |
| 192 | |
| 193 | switch (bkup_boot) { |
| 194 | case BACKUP_BOOT_DEVICE_USB: |
| 195 | return BOOT_DEVICE_DFU; |
| 196 | case BACKUP_BOOT_DEVICE_UART: |
| 197 | return BOOT_DEVICE_UART; |
| 198 | case BACKUP_BOOT_DEVICE_ETHERNET: |
| 199 | return BOOT_DEVICE_ETHERNET; |
| 200 | case BACKUP_BOOT_DEVICE_MMC2: |
| 201 | { |
| 202 | u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >> |
| 203 | MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT; |
| 204 | if (port == 0x0) |
| 205 | return BOOT_DEVICE_MMC1; |
| 206 | return BOOT_DEVICE_MMC2; |
| 207 | } |
| 208 | case BACKUP_BOOT_DEVICE_SPI: |
| 209 | return BOOT_DEVICE_SPI; |
| 210 | case BACKUP_BOOT_DEVICE_I2C: |
| 211 | return BOOT_DEVICE_I2C; |
| 212 | } |
| 213 | |
| 214 | return BOOT_DEVICE_RAM; |
| 215 | } |
| 216 | |
| 217 | static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat) |
| 218 | { |
| 219 | u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> |
| 220 | WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; |
| 221 | |
| 222 | bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << |
| 223 | BOOT_MODE_B_SHIFT; |
| 224 | |
| 225 | if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI || |
| 226 | bootmode == BOOT_DEVICE_XSPI) |
| 227 | bootmode = BOOT_DEVICE_SPI; |
| 228 | |
| 229 | if (bootmode == BOOT_DEVICE_MMC2) { |
| 230 | u32 port = (main_devstat & |
| 231 | MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >> |
| 232 | MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT; |
| 233 | if (port == 0x0) |
| 234 | bootmode = BOOT_DEVICE_MMC1; |
| 235 | } |
| 236 | |
| 237 | return bootmode; |
| 238 | } |
| 239 | |
| 240 | u32 spl_boot_device(void) |
| 241 | { |
| 242 | u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); |
| 243 | u32 main_devstat; |
| 244 | |
| 245 | if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) { |
| 246 | printf("ERROR: MCU only boot is not yet supported\n"); |
| 247 | return BOOT_DEVICE_RAM; |
| 248 | } |
| 249 | |
| 250 | /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */ |
| 251 | main_devstat = readl(CTRLMMR_MAIN_DEVSTAT); |
| 252 | |
| 253 | if (bootindex == K3_PRIMARY_BOOTMODE) |
| 254 | return __get_primary_bootmedia(main_devstat, wkup_devstat); |
| 255 | else |
| 256 | return __get_backup_bootmedia(main_devstat); |
| 257 | } |
| 258 | #endif |
| 259 | |
| 260 | #define J721S2_DEV_MCU_RTI0 295 |
| 261 | #define J721S2_DEV_MCU_RTI1 296 |
| 262 | #define J721S2_DEV_MCU_ARMSS0_CPU0 284 |
| 263 | #define J721S2_DEV_MCU_ARMSS0_CPU1 285 |
| 264 | |
| 265 | void release_resources_for_core_shutdown(void) |
| 266 | { |
| 267 | if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) { |
| 268 | struct ti_sci_handle *ti_sci; |
| 269 | struct ti_sci_dev_ops *dev_ops; |
| 270 | struct ti_sci_proc_ops *proc_ops; |
| 271 | int ret; |
| 272 | u32 i; |
| 273 | |
| 274 | const u32 put_device_ids[] = { |
| 275 | J721S2_DEV_MCU_RTI0, |
| 276 | J721S2_DEV_MCU_RTI1, |
| 277 | }; |
| 278 | |
| 279 | ti_sci = get_ti_sci_handle(); |
| 280 | dev_ops = &ti_sci->ops.dev_ops; |
| 281 | proc_ops = &ti_sci->ops.proc_ops; |
| 282 | |
| 283 | /* Iterate through list of devices to put (shutdown) */ |
| 284 | for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { |
| 285 | u32 id = put_device_ids[i]; |
| 286 | |
| 287 | ret = dev_ops->put_device(ti_sci, id); |
| 288 | if (ret) |
| 289 | panic("Failed to put device %u (%d)\n", id, ret); |
| 290 | } |
| 291 | |
| 292 | const u32 put_core_ids[] = { |
| 293 | J721S2_DEV_MCU_ARMSS0_CPU1, |
| 294 | J721S2_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ |
| 295 | }; |
| 296 | |
| 297 | /* Iterate through list of cores to put (shutdown) */ |
| 298 | for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { |
| 299 | u32 id = put_core_ids[i]; |
| 300 | |
| 301 | /* |
| 302 | * Queue up the core shutdown request. Note that this call |
| 303 | * needs to be followed up by an actual invocation of an WFE |
| 304 | * or WFI CPU instruction. |
| 305 | */ |
| 306 | ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); |
| 307 | if (ret) |
| 308 | panic("Failed sending core %u shutdown message (%d)\n", |
| 309 | id, ret); |
| 310 | } |
| 311 | } |
| 312 | } |