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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Marek Vasutc140e982011-11-08 23:18:08 +00002/*
Otavio Salvador90818622013-01-19 16:02:49 +00003 * Freescale i.MX23/i.MX28 Clock
Marek Vasutc140e982011-11-08 23:18:08 +00004 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
Marek Vasutc140e982011-11-08 23:18:08 +00007 */
8
9#ifndef __CLOCK_H__
10#define __CLOCK_H__
11
12enum mxc_clock {
13 MXC_ARM_CLK = 0,
14 MXC_AHB_CLK,
15 MXC_IPG_CLK,
16 MXC_EMI_CLK,
17 MXC_GPMI_CLK,
18 MXC_IO0_CLK,
19 MXC_IO1_CLK,
Otavio Salvador90818622013-01-19 16:02:49 +000020 MXC_XTAL_CLK,
Marek Vasutc140e982011-11-08 23:18:08 +000021 MXC_SSP0_CLK,
Otavio Salvador90818622013-01-19 16:02:49 +000022#ifdef CONFIG_MX28
Marek Vasutc140e982011-11-08 23:18:08 +000023 MXC_SSP1_CLK,
24 MXC_SSP2_CLK,
25 MXC_SSP3_CLK,
Otavio Salvador90818622013-01-19 16:02:49 +000026#endif
Marek Vasutc140e982011-11-08 23:18:08 +000027};
28
29enum mxs_ioclock {
30 MXC_IOCLK0 = 0,
31 MXC_IOCLK1,
32};
33
34enum mxs_sspclock {
35 MXC_SSPCLK0 = 0,
Otavio Salvador90818622013-01-19 16:02:49 +000036#ifdef CONFIG_MX28
Marek Vasutc140e982011-11-08 23:18:08 +000037 MXC_SSPCLK1,
38 MXC_SSPCLK2,
39 MXC_SSPCLK3,
Otavio Salvador90818622013-01-19 16:02:49 +000040#endif
Marek Vasutc140e982011-11-08 23:18:08 +000041};
42
43uint32_t mxc_get_clock(enum mxc_clock clk);
44
Otavio Salvador2906f942013-01-11 03:19:03 +000045void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
46void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
47void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
Peng Fan93320422015-10-29 15:54:39 +080048void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq);
Marek Vasutc140e982011-11-08 23:18:08 +000049
50/* Compatibility with the FEC Ethernet driver */
51#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
52
53#endif /* __CLOCK_H__ */