Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 2 | /* |
Priyanka Jain | 88c2566 | 2018-10-29 09:11:29 +0000 | [diff] [blame] | 3 | * Copyright 2017-2018 NXP |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 4 | * Copyright 2014-2015, Freescale Semiconductor |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _FSL_LAYERSCAPE_CPU_H |
| 8 | #define _FSL_LAYERSCAPE_CPU_H |
| 9 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 10 | #ifdef CONFIG_FSL_LSCH3 |
| 11 | #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 |
| 12 | #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 |
| 13 | #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 |
| 14 | #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 |
Priyanka Jain | 88c2566 | 2018-10-29 09:11:29 +0000 | [diff] [blame] | 15 | #ifndef CONFIG_NXP_LSCH3_2 |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 16 | #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 |
| 17 | #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 |
| 18 | #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 |
Priyanka Jain | 88c2566 | 2018-10-29 09:11:29 +0000 | [diff] [blame] | 19 | #endif |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 20 | #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 |
| 21 | #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 |
| 22 | #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 |
| 23 | #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 |
Priyanka Jain | 88c2566 | 2018-10-29 09:11:29 +0000 | [diff] [blame] | 24 | #ifndef CONFIG_NXP_LSCH3_2 |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 25 | #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 |
| 26 | #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 |
Priyanka Jain | 88c2566 | 2018-10-29 09:11:29 +0000 | [diff] [blame] | 27 | #endif |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 28 | #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 |
| 29 | #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 |
| 30 | #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 |
| 31 | #define CONFIG_SYS_FSL_MC_SIZE 0x4000000 |
| 32 | #define CONFIG_SYS_FSL_NI_BASE 0x810000000 |
| 33 | #define CONFIG_SYS_FSL_NI_SIZE 0x8000000 |
| 34 | #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 |
| 35 | #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 |
| 36 | #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 |
| 37 | #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 |
| 38 | #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 |
| 39 | #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 |
| 40 | #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 |
| 41 | #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 |
| 42 | #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 |
| 43 | #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 |
| 44 | #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 |
Priyanka Jain | b795ff0 | 2018-11-28 09:56:46 +0000 | [diff] [blame] | 45 | #ifndef CONFIG_ARCH_LX2160A |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 46 | #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 |
Priyanka Jain | b795ff0 | 2018-11-28 09:56:46 +0000 | [diff] [blame] | 47 | #else |
| 48 | #define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000 |
| 49 | #endif |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 50 | #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 |
Priyanka Jain | 88c2566 | 2018-10-29 09:11:29 +0000 | [diff] [blame] | 51 | #ifdef CONFIG_NXP_LSCH3_2 |
| 52 | #define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 |
| 53 | #define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 |
| 54 | #define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 |
| 55 | #define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 |
| 56 | #else |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 57 | #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 |
| 58 | #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 |
Priyanka Jain | 88c2566 | 2018-10-29 09:11:29 +0000 | [diff] [blame] | 59 | #endif |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 60 | #elif defined(CONFIG_FSL_LSCH2) |
| 61 | #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 |
| 62 | #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 |
| 63 | #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 |
| 64 | #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 |
| 65 | #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 |
| 66 | #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 |
| 67 | #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 |
| 68 | #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 |
| 69 | #define CONFIG_SYS_FSL_IFC_BASE 0x60000000 |
| 70 | #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 |
| 71 | #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 |
| 72 | #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 |
| 73 | #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 |
| 74 | #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 |
| 75 | #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 |
| 76 | #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ |
| 77 | #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 |
| 78 | #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 |
| 79 | #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 |
| 80 | #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 |
| 81 | #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 82 | #endif |
| 83 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 84 | int fsl_qoriq_core_to_cluster(unsigned int core); |
| 85 | u32 cpu_mask(void); |
Simon Glass | 243182c | 2017-05-17 08:23:06 -0600 | [diff] [blame] | 86 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 87 | #endif /* _FSL_LAYERSCAPE_CPU_H */ |