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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hu0e58b512015-10-26 19:47:50 +08002/*
Priyanka Jain88c25662018-10-29 09:11:29 +00003 * Copyright 2017-2018 NXP
Mingkai Hu0e58b512015-10-26 19:47:50 +08004 * Copyright 2014-2015, Freescale Semiconductor
Mingkai Hu0e58b512015-10-26 19:47:50 +08005 */
6
7#ifndef _FSL_LAYERSCAPE_CPU_H
8#define _FSL_LAYERSCAPE_CPU_H
9
Mingkai Hu0e58b512015-10-26 19:47:50 +080010#ifdef CONFIG_FSL_LSCH3
11#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
12#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
13#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
14#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
Priyanka Jain88c25662018-10-29 09:11:29 +000015#ifndef CONFIG_NXP_LSCH3_2
Mingkai Hu0e58b512015-10-26 19:47:50 +080016#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
17#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
18#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
Priyanka Jain88c25662018-10-29 09:11:29 +000019#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +080020#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
21#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
22#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
23#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
Priyanka Jain88c25662018-10-29 09:11:29 +000024#ifndef CONFIG_NXP_LSCH3_2
Mingkai Hu0e58b512015-10-26 19:47:50 +080025#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
26#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
Priyanka Jain88c25662018-10-29 09:11:29 +000027#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +080028#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
29#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
30#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
31#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
32#define CONFIG_SYS_FSL_NI_BASE 0x810000000
33#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
34#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
35#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
36#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
37#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
38#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
39#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
40#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
41#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
42#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
43#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
44#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
Priyanka Jainb795ff02018-11-28 09:56:46 +000045#ifndef CONFIG_ARCH_LX2160A
Mingkai Hu0e58b512015-10-26 19:47:50 +080046#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
Priyanka Jainb795ff02018-11-28 09:56:46 +000047#else
48#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
49#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +080050#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
Priyanka Jain88c25662018-10-29 09:11:29 +000051#ifdef CONFIG_NXP_LSCH3_2
52#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
53#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000
54#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000
55#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000
56#else
Mingkai Hu0e58b512015-10-26 19:47:50 +080057#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
58#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
Priyanka Jain88c25662018-10-29 09:11:29 +000059#endif
Mingkai Hue4e93ea2015-10-26 19:47:51 +080060#elif defined(CONFIG_FSL_LSCH2)
61#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
62#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
63#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
64#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
65#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
66#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
67#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
68#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
69#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
70#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
71#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
72#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
73#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
74#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
75#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
76#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
77#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
78#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
79#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
80#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
81#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
Mingkai Hu0e58b512015-10-26 19:47:50 +080082#endif
83
Mingkai Hu0e58b512015-10-26 19:47:50 +080084int fsl_qoriq_core_to_cluster(unsigned int core);
85u32 cpu_mask(void);
Simon Glass243182c2017-05-17 08:23:06 -060086
Mingkai Hu0e58b512015-10-26 19:47:50 +080087#endif /* _FSL_LAYERSCAPE_CPU_H */