Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 1e73639b5dbcb1f93b6d6b37e4b970ac5122b672 / . / drivers / clk / mediatek / clk-mt7986.c
blob: efc3d4120b78554ed7faf04de814eb0e79bafeab [file] [log] [blame]
developer37161fe2022-09-09 20:00:09 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek clock driver for MT7986 SoC
4 *
5 * Copyright (C) 2022 MediaTek Inc.
6 * Author: Sam Shih <sam.shih@mediatek.com>
7 */
8
9#include <dm.h>
10#include <log.h>
11#include <asm/arch-mediatek/reset.h>
12#include <asm/io.h>
13#include <dt-bindings/clock/mt7986-clk.h>
14#include <linux/bitops.h>
15
16#include "clk-mtk.h"
17
18#define MT7986_CLK_PDN 0x250
19#define MT7986_CLK_PDN_EN_WRITE BIT(31)
20
21#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
22 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
23
24#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \
25 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
26
27#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \
28 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
29
30/* FIXED PLLS */
31static const struct mtk_fixed_clk fixed_pll_clks[] = {
32 FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
33 FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
34 FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
35 FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
36 FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
37 FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
38 FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
39 FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
40};
41
42/* TOPCKGEN FIXED CLK */
43static const struct mtk_fixed_clk top_fixed_clks[] = {
44 FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
45};
46
47/* TOPCKGEN FIXED DIV */
48static const struct mtk_fixed_factor top_fixed_divs[] = {
49 PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
50 PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
51 PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
52 PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
53 PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
54 PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
55 PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
56 PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
57 PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
58 PLL_FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", CK_APMIXED_MMPLL, 1, 16),
59 PLL_FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", CK_APMIXED_MMPLL, 1, 8),
60 PLL_FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", CK_APMIXED_MMPLL, 1, 30),
61 PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
62 1),
63 PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
64 PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
65 PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
66 PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
67 PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
68 PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
69 PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
70 PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
71 1),
72 PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
73 PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
74 PLL_FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
75 PLL_FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m",
76 CK_APMIXED_WEDMCUPLL, 1, 1),
77 PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
78 10),
79 PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
80 TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M,
81 1, 2),
82 TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
83 1250),
84 TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
85 1220),
86 TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
87 TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
88 1),
89 TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
90 TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
91 TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
92 TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
93 TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
94 TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
95 TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
96 TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
97 TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
98 1),
99 TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
100 TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
101 CK_TOP_NETSYS_MCU_SEL, 1, 1),
102 TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
103 TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
104 TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
105 TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
106 TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
107 TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
108 TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
109 TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
110 TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
111 TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
112 TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
113 1),
114};
115
116/* TOPCKGEN MUX PARENTS */
117static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D8,
118 CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2,
119 CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2,
120 CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 };
121
122static const int spinfi_parents[] = {
123 CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
124 CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2,
125 CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8
126};
127
128static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
129 CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2,
130 CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4,
131 CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 };
132
133static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
134 CK_TOP_M_D8_D2 };
135
136static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
137 CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
138
139static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
140 CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
141
142static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
143 CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2,
144 CK_TOP_CB_RTC_32K };
145
146static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
147 CK_TOP_NET1_D5_D2 };
148
149static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M };
150
151static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
152
153static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 };
154
155static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
156 CK_TOP_CB_NET2_D4 };
157
158static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2,
159 CK_TOP_NET2_D4_D2 };
160
161static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
162 CK_TOP_NET2_D3_D2 };
163
164static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M };
165
166static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 };
167
168static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
169 CK_TOP_CB_NET1_D5 };
170
171static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M,
172 CK_TOP_CB_WEDMCU_760M,
173 CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4,
174 CK_TOP_CB_NET1_D5 };
175
176static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
177 CK_TOP_CB_NET2_800M,
178 CK_TOP_CB_WEDMCU_760M,
179 CK_TOP_CB_MM_D2 };
180
181static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
182 CK_TOP_CB_SGM_325M };
183
184static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 };
185
186static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
187
188static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M,
189 CK_TOP_CB_MM_D2 };
190
191static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M };
192
193static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
194 CK_TOP_M_D8_D2 };
195
196static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
197 CK_TOP_M_D8_D2 };
198
199static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
200
201static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M,
202 CK_TOP_CB_U2_PHYD_CK };
203
204#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
205 _shift, _width, _gate, _upd_ofs, _upd) \
206 { \
207 .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \
208 .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
209 .upd_shift = _upd, .mux_shift = _shift, \
210 .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
211 .gate_shift = _gate, .parent = _parents, \
212 .num_parents = ARRAY_SIZE(_parents), \
213 .flags = CLK_MUX_SETCLR_UPD, \
214 }
215
216/* TOPCKGEN MUX_GATE */
217static const struct mtk_composite top_muxes[] = {
218 /* CLK_CFG_0 */
219 TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
220 0x008, 0, 3, 7, 0x1C0, 0),
221 TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
222 0x008, 8, 3, 15, 0x1C0, 1),
223 TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
224 3, 23, 0x1C0, 2),
225 TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
226 0x008, 24, 3, 31, 0x1C0, 3),
227 /* CLK_CFG_1 */
228 TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
229 0, 2, 7, 0x1C0, 4),
230 TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
231 2, 15, 0x1C0, 5),
232 TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
233 2, 23, 0x1C0, 6),
234 TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
235 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7),
236 /* CLK_CFG_2 */
237 TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
238 0x024, 0x028, 0, 1, 7, 0x1C0, 8),
239 TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
240 0x024, 0x028, 8, 1, 15, 0x1C0, 9),
241 TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
242 0x024, 0x028, 16, 1, 23, 0x1C0, 10),
243 TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
244 0x028, 24, 1, 31, 0x1C0, 11),
245 /* CLK_CFG_3 */
246 TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
247 0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12),
248 TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
249 0x038, 8, 2, 15, 0x1C0, 13),
250 TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
251 0x038, 16, 2, 23, 0x1C0, 14),
252 TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
253 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15),
254 /* CLK_CFG_4 */
255 TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
256 0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16),
257 TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
258 0x048, 8, 1, 15, 0x1C0, 17),
259 TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
260 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
261 TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
262 0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
263 /* CLK_CFG_5 */
264 TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
265 0x054, 0x058, 0, 2, 7, 0x1C0, 20),
266 TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
267 0x054, 0x058, 8, 1, 15, 0x1C0, 21),
268 TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
269 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
270 TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
271 0x058, 24, 1, 31, 0x1C0, 23),
272 /* CLK_CFG_6 */
273 TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
274 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
275 TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
276 0x068, 8, 1, 15, 0x1C0, 25),
277 TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
278 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
279 TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
280 0x064, 0x068, 24, 1, 31, 0x1C0, 27),
281 /* CLK_CFG_7 */
282 TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
283 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
284 TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
285 0x078, 8, 2, 15, 0x1C0, 29),
286 TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
287 0x074, 0x078, 16, 2, 23, 0x1C0, 30),
288 TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
289 0x078, 24, 1, 31, 0x1C4, 0),
290 /* CLK_CFG_8 */
291 TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
292 0x084, 0x088, 0, 1, 7, 0x1C4, 1),
293 TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
294 0x084, 0x088, 8, 1, 15, 0x1C4, 2),
295 TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
296 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
297 TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
298 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
299 /* CLK_CFG_9 */
300 TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
301 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
302};
303
304/* INFRA FIXED DIV */
305static const struct mtk_fixed_factor infra_fixed_divs[] = {
306 TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
307 TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
308 TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
309 TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
310 TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1),
311 TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
312 TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
313 TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
314 1),
315 TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
316 INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
317 1),
318 INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
319 1),
320 INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
321 1),
322 TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
323 TOP_FACTOR(CK_INFRA_EIP_CK, "infra_eip", CK_TOP_EIP_B, 1, 1),
324 INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
325 1),
326 TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
327 TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
328 TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
329 1),
330 TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
331 INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
332 1, 1),
333 INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
334 1, 1),
335 INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
336 1, 1),
337 TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
338 TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
339 INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
340 1),
341 INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
342 1),
343 TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
344 TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_416M, 1, 1),
345 TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_250M,
346 1, 1),
347 TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
348 TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
349 TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
350 TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
351 TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
352 1),
353 TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
354 CK_TOP_PEXTP_TL, 1, 1),
355 TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
356 TOP_FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", CK_TOP_SYSAXI, 1, 1),
357};
358
359/* INFRASYS MUX PARENTS */
360static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
361
362static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
363
364static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
365
366static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K,
367 CK_INFRA_CK_F26M,
368 CK_INFRA_66M_MCK, CK_INFRA_PWM };
369
370static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
371 -1, CK_INFRA_PCIE_CK };
372
373#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
374 { \
375 .id = _id, .mux_reg = (_reg) + 0x8, \
376 .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
377 .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
378 .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
379 .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
380 }
381
382/* INFRA MUX */
383
384static const struct mtk_composite infra_muxes[] = {
385 /* MODULE_CLK_SEL_0 */
386 INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
387 0x10, 0, 1),
388 INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
389 0x10, 1, 1),
390 INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
391 0x10, 2, 1),
392 INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
393 4, 1),
394 INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
395 5, 1),
396 INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
397 0x10, 9, 2),
398 INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
399 0x10, 11, 2),
400 INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
401 0x10, 13, 2),
402 /* MODULE_CLK_SEL_1 */
403 INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
404 0, 2),
405};
406
407static const struct mtk_gate_regs infra_0_cg_regs = {
408 .set_ofs = 0x40,
409 .clr_ofs = 0x44,
410 .sta_ofs = 0x48,
411};
412
413static const struct mtk_gate_regs infra_1_cg_regs = {
414 .set_ofs = 0x50,
415 .clr_ofs = 0x54,
416 .sta_ofs = 0x58,
417};
418
419static const struct mtk_gate_regs infra_2_cg_regs = {
420 .set_ofs = 0x60,
421 .clr_ofs = 0x64,
422 .sta_ofs = 0x68,
423};
424
425#define GATE_INFRA0(_id, _name, _parent, _shift) \
426 { \
427 .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
428 .shift = _shift, \
429 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
430 }
431
432#define GATE_INFRA1(_id, _name, _parent, _shift) \
433 { \
434 .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
435 .shift = _shift, \
436 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
437 }
438
439#define GATE_INFRA2(_id, _name, _parent, _shift) \
440 { \
441 .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
442 .shift = _shift, \
443 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
444 }
445
446/* INFRA GATE */
447
448static const struct mtk_gate infracfg_ao_gates[] = {
449 /* INFRA0 */
450 GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
451 GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
452 GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
453 GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
454 GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
455 GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
456 GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", CK_INFRA_EIP_CK, 7),
457 GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
458 GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
459 GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
460 GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
461 11),
462 GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
463 13),
464 GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
465 14),
466 GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
467 GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
468 GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
469 GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
470 GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26),
471 /* INFRA1 */
472 GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
473 GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
474 GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
475 GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
476 GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
477 GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
478 GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
479 9),
480 GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
481 GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
482 GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
483 GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
484 13),
485 GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
486 14),
487 GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
488 GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
489 GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
490 CK_INFRA_FMSDC_HCK_CK, 17),
491 GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
492 CK_INFRA_PERI_133M, 18),
493 GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
494 19),
495 GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_CK_F26M, 20),
496 GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21),
497 GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
498 23),
499 /* INFRA2 */
500 GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
501 0),
502 GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
503 1),
504 GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
505 2),
506 GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
507 GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13),
508 GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15),
509 GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
510};
511
512static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
513 .fdivs_offs = CLK_APMIXED_NR_CLK,
514 .xtal_rate = 40 * MHZ,
515 .fclks = fixed_pll_clks,
516};
517
518static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
519 .fdivs_offs = CK_TOP_CB_M_416M,
520 .muxes_offs = CK_TOP_NFI1X_SEL,
521 .fclks = top_fixed_clks,
522 .fdivs = top_fixed_divs,
523 .muxes = top_muxes,
524 .flags = CLK_BYPASS_XTAL,
525};
526
527static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
528 .fdivs_offs = CK_INFRA_CK_F26M,
529 .muxes_offs = CK_INFRA_UART0_SEL,
530 .fdivs = infra_fixed_divs,
531 .muxes = infra_muxes,
532};
533
534static const struct udevice_id mt7986_fixed_pll_compat[] = {
535 { .compatible = "mediatek,mt7986-fixed-plls" },
Christian Marangi4dd4a282024-06-24 23:03:40 +0200[diff] [blame]536 { .compatible = "mediatek,mt7986-apmixedsys" },
developer37161fe2022-09-09 20:00:09 +0800[diff] [blame]537 {}
538};
539
540static const struct udevice_id mt7986_topckgen_compat[] = {
541 { .compatible = "mediatek,mt7986-topckgen" },
542 {}
543};
544
545static int mt7986_fixed_pll_probe(struct udevice *dev)
546{
547 return mtk_common_clk_init(dev, &mt7986_fixed_pll_clk_tree);
548}
549
550static int mt7986_topckgen_probe(struct udevice *dev)
551{
552 struct mtk_clk_priv *priv = dev_get_priv(dev);
553
554 priv->base = dev_read_addr_ptr(dev);
555 writel(MT7986_CLK_PDN_EN_WRITE, priv->base + MT7986_CLK_PDN);
556
557 return mtk_common_clk_init(dev, &mt7986_topckgen_clk_tree);
558}
559
560U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
561 .name = "mt7986-clock-fixed-pll",
562 .id = UCLASS_CLK,
563 .of_match = mt7986_fixed_pll_compat,
564 .probe = mt7986_fixed_pll_probe,
565 .priv_auto = sizeof(struct mtk_clk_priv),
566 .ops = &mtk_clk_topckgen_ops,
567 .flags = DM_FLAG_PRE_RELOC,
568};
569
570U_BOOT_DRIVER(mtk_clk_topckgen) = {
571 .name = "mt7986-clock-topckgen",
572 .id = UCLASS_CLK,
573 .of_match = mt7986_topckgen_compat,
574 .probe = mt7986_topckgen_probe,
575 .priv_auto = sizeof(struct mtk_clk_priv),
576 .ops = &mtk_clk_topckgen_ops,
577 .flags = DM_FLAG_PRE_RELOC,
578};
579
580static const struct udevice_id mt7986_infracfg_compat[] = {
581 { .compatible = "mediatek,mt7986-infracfg" },
582 {}
583};
584
585static const struct udevice_id mt7986_infracfg_ao_compat[] = {
586 { .compatible = "mediatek,mt7986-infracfg_ao" },
587 {}
588};
589
590static int mt7986_infracfg_probe(struct udevice *dev)
591{
592 return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
593}
594
595static int mt7986_infracfg_ao_probe(struct udevice *dev)
596{
597 return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree,
598 infracfg_ao_gates);
599}
600
601U_BOOT_DRIVER(mtk_clk_infracfg) = {
602 .name = "mt7986-clock-infracfg",
603 .id = UCLASS_CLK,
604 .of_match = mt7986_infracfg_compat,
605 .probe = mt7986_infracfg_probe,
606 .priv_auto = sizeof(struct mtk_clk_priv),
607 .ops = &mtk_clk_infrasys_ops,
608 .flags = DM_FLAG_PRE_RELOC,
609};
610
611U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
612 .name = "mt7986-clock-infracfg-ao",
613 .id = UCLASS_CLK,
614 .of_match = mt7986_infracfg_ao_compat,
615 .probe = mt7986_infracfg_ao_probe,
616 .priv_auto = sizeof(struct mtk_cg_priv),
617 .ops = &mtk_clk_gate_ops,
618 .flags = DM_FLAG_PRE_RELOC,
619};
620
621/* ethsys */
622static const struct mtk_gate_regs eth_cg_regs = {
623 .sta_ofs = 0x30,
624};
625
626#define GATE_ETH(_id, _name, _parent, _shift) \
627 { \
628 .id = _id, .parent = _parent, .regs = &eth_cg_regs, \
629 .shift = _shift, \
630 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
631 }
632
633static const struct mtk_gate eth_cgs[] = {
634 GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7),
635 GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8),
636 GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
637 GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 14),
638 GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
639};
640
641static int mt7986_ethsys_probe(struct udevice *dev)
642{
643 return mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree,
644 eth_cgs);
645}
646
647static int mt7986_ethsys_bind(struct udevice *dev)
648{
649 int ret = 0;
650
651 if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
652 ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
653 if (ret)
654 debug("Warning: failed to bind reset controller\n");
655 }
656
657 return ret;
658}
659
660static const struct udevice_id mt7986_ethsys_compat[] = {
661 { .compatible = "mediatek,mt7986-ethsys" },
662 { }
663};
664
665U_BOOT_DRIVER(mtk_clk_ethsys) = {
666 .name = "mt7986-clock-ethsys",
667 .id = UCLASS_CLK,
668 .of_match = mt7986_ethsys_compat,
669 .probe = mt7986_ethsys_probe,
670 .bind = mt7986_ethsys_bind,
671 .priv_auto = sizeof(struct mtk_cg_priv),
672 .ops = &mtk_clk_gate_ops,
673};