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git01.mediatek.com / filogic / uboot / 1e2b01057abcd63c5cddd13da874123d5905cb54 / . / arch / arm / dts / imx6qdl-aristainetos2.dtsi
blob: da6ab63808db6fac0af25db9fdde0f52222ec3b5 [file] [log] [blame]
Heiko Schocher1e2b0102019-12-01 11:23:09 +0100[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0)
2/*
3 * support for the imx6 based aristainetos2 board
4 *
5 * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
6 * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
7 *
8 */
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/clock/imx6qdl-clock.h>
11
12/ {
13 backlight: backlight {
14 compatible = "pwm-backlight";
15 pwms = <&pwm1 0 5000000>;
16 brightness-levels = <0 4 8 16 32 64 128 255>;
17 default-brightness-level = <7>;
18 enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
19 };
20
21 reg_2p5v: regulator-2p5v {
22 compatible = "regulator-fixed";
23 regulator-name = "2P5V";
24 regulator-min-microvolt = <2500000>;
25 regulator-max-microvolt = <2500000>;
26 regulator-always-on;
27 };
28
29 reg_3p3v: regulator-3p3v {
30 compatible = "regulator-fixed";
31 regulator-name = "3P3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 regulator-always-on;
35 };
36
37 reg_usbh1_vbus: regulator-usbh1-vbus {
38 compatible = "regulator-fixed";
39 enable-active-high;
40 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>;
43 regulator-name = "usb_h1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 };
47
48 reg_usbotg_vbus: regulator-usbotg-vbus {
49 compatible = "regulator-fixed";
50 enable-active-high;
51 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>;
54 regulator-name = "usb_otg_vbus";
55 regulator-min-microvolt = <5000000>;
56 regulator-max-microvolt = <5000000>;
57 };
58};
59
60&audmux {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_audmux>;
63 status = "okay";
64};
65
66&can1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_flexcan1>;
69 status = "okay";
70};
71
72&can2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_flexcan2>;
75 status = "okay";
76};
77
78&ecspi1 {
79 cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
80 &gpio4 10 GPIO_ACTIVE_HIGH
81 &gpio4 11 GPIO_ACTIVE_HIGH>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_ecspi1>;
84 status = "okay";
85};
86
87&ecspi2 {
88 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_ecspi2>;
91 status = "okay";
92};
93
94&ecspi4 {
95 cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_ecspi4>;
98 status = "okay";
99
100 flash: m25p80@1 {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "micron,n25q128a11", "jedec,spi-nor";
104 spi-max-frequency = <20000000>;
105 reg = <1>;
106 };
107};
108
109&i2c1 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_i2c1>;
112 status = "okay";
113
114 pmic@58 {
115 compatible = "dlg,da9063";
116 reg = <0x58>;
117 interrupt-parent = <&gpio1>;
118 interrupts = <04 0x8>;
119
120 regulators {
121 bcore1 {
122 regulator-name = "bcore1";
123 regulator-always-on = <1>;
124 regulator-min-microvolt = <300000>;
125 regulator-max-microvolt = <3300000>;
126 };
127
128 bcore2 {
129 regulator-name = "bcore2";
130 regulator-always-on = <1>;
131 regulator-min-microvolt = <300000>;
132 regulator-max-microvolt = <3300000>;
133 };
134
135 bpro {
136 regulator-name = "bpro";
137 regulator-always-on = <1>;
138 regulator-min-microvolt = <300000>;
139 regulator-max-microvolt = <3300000>;
140 };
141
142 bperi {
143 regulator-name = "bperi";
144 regulator-always-on = <1>;
145 regulator-min-microvolt = <300000>;
146 regulator-max-microvolt = <3300000>;
147 };
148
149 bmem {
150 regulator-name = "bmem";
151 regulator-always-on = <1>;
152 regulator-min-microvolt = <300000>;
153 regulator-max-microvolt = <3300000>;
154 };
155
156 ldo2 {
157 regulator-name = "ldo2";
158 regulator-always-on = <1>;
159 regulator-min-microvolt = <300000>;
160 regulator-max-microvolt = <1800000>;
161 };
162
163 ldo3 {
164 regulator-name = "ldo3";
165 regulator-always-on = <1>;
166 regulator-min-microvolt = <300000>;
167 regulator-max-microvolt = <3300000>;
168 };
169
170 ldo4 {
171 regulator-name = "ldo4";
172 regulator-always-on = <1>;
173 regulator-min-microvolt = <300000>;
174 regulator-max-microvolt = <3300000>;
175 };
176
177 ldo5 {
178 regulator-name = "ldo5";
179 regulator-always-on = <1>;
180 regulator-min-microvolt = <300000>;
181 regulator-max-microvolt = <3300000>;
182 };
183
184 ldo6 {
185 regulator-name = "ldo6";
186 regulator-always-on = <1>;
187 regulator-min-microvolt = <300000>;
188 regulator-max-microvolt = <3300000>;
189 };
190
191 ldo7 {
192 regulator-name = "ldo7";
193 regulator-always-on = <1>;
194 regulator-min-microvolt = <300000>;
195 regulator-max-microvolt = <3300000>;
196 };
197
198 ldo8 {
199 regulator-name = "ldo8";
200 regulator-always-on = <1>;
201 regulator-min-microvolt = <300000>;
202 regulator-max-microvolt = <3300000>;
203 };
204
205 ldo9 {
206 regulator-name = "ldo9";
207 regulator-always-on = <1>;
208 regulator-min-microvolt = <300000>;
209 regulator-max-microvolt = <3300000>;
210 };
211
212 ldo10 {
213 regulator-name = "ldo10";
214 regulator-always-on = <1>;
215 regulator-min-microvolt = <300000>;
216 regulator-max-microvolt = <3300000>;
217 };
218
219 ldo11 {
220 regulator-name = "ldo11";
221 regulator-always-on = <1>;
222 regulator-min-microvolt = <300000>;
223 regulator-max-microvolt = <3300000>;
224 };
225
226 bio {
227 regulator-name = "bio";
228 regulator-always-on = <1>;
229 regulator-min-microvolt = <1800000>;
230 regulator-max-microvolt = <1800000>;
231 };
232 };
233 };
234
235 tmp103: tmp103@71 {
236 compatible = "ti,tmp103";
237 reg = <0x71>;
238 };
239};
240
241&i2c2 {
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_i2c2>;
244 status = "okay";
245};
246
247&i2c3 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_i2c3>;
250 status = "okay";
251
252 expander: tca6416@20 {
253 compatible = "ti,tca6416";
254 reg = <0x20>;
255 #gpio-cells = <2>;
256 gpio-controller;
257 };
258
259 rtc@68 {
260 compatible = "dallas,m41t00";
261 reg = <0x68>;
262 };
263};
264
265&i2c4 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_i2c4>;
268 status = "okay";
269
270 eeprom@50{
271 compatible = "atmel,24c64";
272 reg = <0x50>;
273 };
274
275 eeprom@57{
276 compatible = "atmel,24c64";
277 reg = <0x57>;
278 };
279};
280
281&fec {
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_enet>;
284 phy-mode = "rgmii";
285 phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>;
286 txd0-skew-ps = <0>;
287 txd1-skew-ps = <0>;
288 txd2-skew-ps = <0>;
289 txd3-skew-ps = <0>;
290 status = "okay";
291};
292
293&gpmi {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_gpmi_nand>;
296 status = "okay";
297};
298
299&pcie {
300 reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>;
301 status = "okay";
302};
303
304&pwm1 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_pwm1>;
307 status = "okay";
308};
309
310&uart1 {
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_uart1>;
313 uart-has-rtscts;
314 status = "okay";
315};
316
317&uart2 {
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_uart2>;
320 status = "okay";
321};
322
323&uart3 {
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_uart3>;
326 uart-has-rtscts;
327 status = "okay";
328};
329
330&uart4 {
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_uart4>;
333 status = "okay";
334};
335
336&usbh1 {
337 vbus-supply = <&reg_usbh1_vbus>;
338 dr_mode = "host";
339 status = "okay";
340};
341
342&usbotg {
343 vbus-supply = <&reg_usbotg_vbus>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_usbotg>;
346 disable-over-current;
347 dr_mode = "host";
348 status = "okay";
349};
350
351&usdhc1 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_usdhc1>;
354 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
355 no-1-8-v;
356 status = "okay";
357};
358
359&usdhc2 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_usdhc2>;
362 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
363 wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
364 no-1-8-v;
365 status = "okay";
366};
367
368&iomuxc {
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_gpio>;
371
372 pinctrl_audmux: audmux {
373 fsl,pins = <
374 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
375 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
376 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
377 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
378 >;
379 };
380
381 pinctrl_ecspi1: ecspi1grp {
382 fsl,pins = <
383 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
384 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
385 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
386 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */
387 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */
388 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */
389 >;
390 };
391
392 pinctrl_ecspi2: ecspi2grp {
393 fsl,pins = <
394 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
395 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
396 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
397 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */
398 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */
399 >;
400 };
401
402 pinctrl_ecspi4: ecspi4grp {
403 fsl,pins = <
404 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
405 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
406 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
407 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
408 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
409 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
410 >;
411 };
412
413 pinctrl_enet: enetgrp {
414 fsl,pins = <
415 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
416 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
417 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
418 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
419 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
420 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
421 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
422 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
423 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
424 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
425 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
426 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
427 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
428 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
429 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
430 >;
431 };
432
433 pinctrl_flexcan1: flexcan1grp {
434 fsl,pins = <
435 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
436 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
437 >;
438 };
439
440 pinctrl_flexcan2: flexcan2grp {
441 fsl,pins = <
442 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
443 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
444 >;
445 };
446
447 pinctrl_gpio: gpiogrp {
448 fsl,pins = <
449 /* led enable */
450 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
451 /* LCD power enable */
452 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
453 /* led yellow */
454 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
455 /* led red */
456 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
457 /* led green */
458 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0
459 /* led blue */
460 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
461 /* Profibus IRQ */
462 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
463 /* FPGA IRQ */
464 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
465 /* spi bus #2 SS driver enable */
466 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
467 /* RST_LOC# PHY reset input (has pull-down!)*/
468 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
469 /* USB_OTG_ID = GPIO1_24*/
470 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x80000000
471 /* Touchscreen IRQ */
472 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
473 /* PCIe reset */
474 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0
475 >;
476 };
477
478 pinctrl_gpmi_nand: gpmi-nand {
479 fsl,pins = <
480 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
481 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
482 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
483 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
484 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
485 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
486 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
487 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
488 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
489 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
490 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
491 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
492 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
493 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
494 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
495 >;
496 };
497
498 pinctrl_i2c1: i2c1grp {
499 fsl,pins = <
500 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
501 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
502 >;
503 };
504
505 pinctrl_i2c2: i2c2grp {
506 fsl,pins = <
507 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
508 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
509 >;
510 };
511
512 pinctrl_i2c3: i2c3grp {
513 fsl,pins = <
514 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
515 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
516 >;
517 };
518
519 pinctrl_i2c4: i2c4grp {
520 fsl,pins = <
521 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
522 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
523 >;
524 };
525
526 pinctrl_pwm1: pwm1grp {
527 fsl,pins = <
528 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0
529 /* backlight enable */
530 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
531 >;
532 };
533
534 pinctrl_uart1: uart1grp {
535 fsl,pins = <
536 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
537 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
538 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
539 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
540 >;
541 };
542
543 pinctrl_uart2: uart2grp {
544 fsl,pins = <
545 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
546 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
547 >;
548 };
549
550 pinctrl_uart3: uart3grp {
551 fsl,pins = <
552 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
553 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
554 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
555 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
556 >;
557 };
558
559 pinctrl_uart4: uart4grp {
560 fsl,pins = <
561 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
562 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
563 >;
564 };
565
566 pinctrl_usbotg: usbotggrp {
567 fsl,pins = <
568 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
569 >;
570 };
571
572 pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus {
573 fsl,pins = <MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0>;
574 };
575
576 pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus {
577 fsl,pins = <MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0>;
578 };
579
580 pinctrl_usdhc1: usdhc1grp {
581 fsl,pins = <
582 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
583 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
584 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
585 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
586 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
587 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
588 /* SD1 card detect input */
589 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
590 /* SD1 write protect input */
591 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
592 >;
593 };
594
595 pinctrl_usdhc2: usdhc2grp {
596 fsl,pins = <
597 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
598 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
599 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
600 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
601 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
602 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
603 /* SD2 level shifter output enable */
604 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0
605 /* SD2 card detect input */
606 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
607 /* SD2 write protect input */
608 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
609 >;
610 };
611};