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git01.mediatek.com / filogic / uboot / 1e088bfad57f9858c230c5aed1e3567d09166774 / . / drivers / qe / qe.h
blob: 0bcd0a9573e8941515c3deeee68d97dd8b448229 [file] [log] [blame]
Dave Liue732e9c2006-11-03 12:11:15 -0600[diff] [blame]1/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __QE_H__
24#define __QE_H__
25
26#include "common.h"
27
28#define QE_NUM_OF_SNUM 28
29#define QE_NUM_OF_BRGS 16
30#define UCC_MAX_NUM 8
31
32#define QE_DATAONLY_BASE (uint)(128)
Dave Liue740c462006-12-07 21:13:15 +0800[diff] [blame]33#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
Dave Liue732e9c2006-11-03 12:11:15 -0600[diff] [blame]34
35/* QE threads SNUM
36*/
37typedef enum qe_snum_state {
38 QE_SNUM_STATE_USED, /* used */
39 QE_SNUM_STATE_FREE /* free */
40} qe_snum_state_e;
41
42typedef struct qe_snum {
43 u8 num; /* snum */
44 qe_snum_state_e state; /* state */
45} qe_snum_t;
46
47/* QE RISC allocation
48*/
49typedef enum qe_risc_allocation {
50 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
51 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
52 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */
53} qe_risc_allocation_e;
54
55/* QE CECR commands for UCC fast.
56*/
57#define QE_CR_FLG 0x00010000
58#define QE_RESET 0x80000000
59#define QE_INIT_TX_RX 0x00000000
60#define QE_INIT_RX 0x00000001
61#define QE_INIT_TX 0x00000002
62#define QE_ENTER_HUNT_MODE 0x00000003
63#define QE_STOP_TX 0x00000004
64#define QE_GRACEFUL_STOP_TX 0x00000005
65#define QE_RESTART_TX 0x00000006
66#define QE_SWITCH_COMMAND 0x00000007
67#define QE_SET_GROUP_ADDRESS 0x00000008
68#define QE_INSERT_CELL 0x00000009
69#define QE_ATM_TRANSMIT 0x0000000a
70#define QE_CELL_POOL_GET 0x0000000b
71#define QE_CELL_POOL_PUT 0x0000000c
72#define QE_IMA_HOST_CMD 0x0000000d
73#define QE_ATM_MULTI_THREAD_INIT 0x00000011
74#define QE_ASSIGN_PAGE 0x00000012
75#define QE_START_FLOW_CONTROL 0x00000014
76#define QE_STOP_FLOW_CONTROL 0x00000015
77#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
78#define QE_GRACEFUL_STOP_RX 0x0000001a
79#define QE_RESTART_RX 0x0000001b
80
81/* QE CECR Sub Block Code - sub block code of QE command.
82*/
83#define QE_CR_SUBBLOCK_INVALID 0x00000000
84#define QE_CR_SUBBLOCK_USB 0x03200000
85#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
86#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
87#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
88#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
89#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
90#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
91#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
92#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
93#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
94#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
95#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
96#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
97#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
98#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
99#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
100#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
101#define QE_CR_SUBBLOCK_MCC1 0x03800000
102#define QE_CR_SUBBLOCK_MCC2 0x03a00000
103#define QE_CR_SUBBLOCK_MCC3 0x03000000
104#define QE_CR_SUBBLOCK_IDMA1 0x02800000
105#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
106#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
107#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
108#define QE_CR_SUBBLOCK_HPAC 0x01e00000
109#define QE_CR_SUBBLOCK_SPI1 0x01400000
110#define QE_CR_SUBBLOCK_SPI2 0x01600000
111#define QE_CR_SUBBLOCK_RAND 0x01c00000
112#define QE_CR_SUBBLOCK_TIMER 0x01e00000
113#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
114
115/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
116*/
117#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
118#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
119#define QE_CR_PROTOCOL_ATM_POS 0x0A
120#define QE_CR_PROTOCOL_ETHERNET 0x0C
121#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
122#define QE_CR_PROTOCOL_SHIFT 6
123
124/* QE ASSIGN PAGE command
125*/
126#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17
127
128/* Communication Direction.
129*/
130typedef enum comm_dir {
131 COMM_DIR_NONE = 0,
132 COMM_DIR_RX = 1,
133 COMM_DIR_TX = 2,
134 COMM_DIR_RX_AND_TX = 3
135} comm_dir_e;
136
137/* Clocks and BRG's
138*/
139typedef enum qe_clock {
140 QE_CLK_NONE = 0,
141 QE_BRG1, /* Baud Rate Generator 1 */
142 QE_BRG2, /* Baud Rate Generator 2 */
143 QE_BRG3, /* Baud Rate Generator 3 */
144 QE_BRG4, /* Baud Rate Generator 4 */
145 QE_BRG5, /* Baud Rate Generator 5 */
146 QE_BRG6, /* Baud Rate Generator 6 */
147 QE_BRG7, /* Baud Rate Generator 7 */
148 QE_BRG8, /* Baud Rate Generator 8 */
149 QE_BRG9, /* Baud Rate Generator 9 */
150 QE_BRG10, /* Baud Rate Generator 10 */
151 QE_BRG11, /* Baud Rate Generator 11 */
152 QE_BRG12, /* Baud Rate Generator 12 */
153 QE_BRG13, /* Baud Rate Generator 13 */
154 QE_BRG14, /* Baud Rate Generator 14 */
155 QE_BRG15, /* Baud Rate Generator 15 */
156 QE_BRG16, /* Baud Rate Generator 16 */
157 QE_CLK1, /* Clock 1 */
158 QE_CLK2, /* Clock 2 */
159 QE_CLK3, /* Clock 3 */
160 QE_CLK4, /* Clock 4 */
161 QE_CLK5, /* Clock 5 */
162 QE_CLK6, /* Clock 6 */
163 QE_CLK7, /* Clock 7 */
164 QE_CLK8, /* Clock 8 */
165 QE_CLK9, /* Clock 9 */
166 QE_CLK10, /* Clock 10 */
167 QE_CLK11, /* Clock 11 */
168 QE_CLK12, /* Clock 12 */
169 QE_CLK13, /* Clock 13 */
170 QE_CLK14, /* Clock 14 */
171 QE_CLK15, /* Clock 15 */
172 QE_CLK16, /* Clock 16 */
173 QE_CLK17, /* Clock 17 */
174 QE_CLK18, /* Clock 18 */
175 QE_CLK19, /* Clock 19 */
176 QE_CLK20, /* Clock 20 */
177 QE_CLK21, /* Clock 21 */
178 QE_CLK22, /* Clock 22 */
179 QE_CLK23, /* Clock 23 */
180 QE_CLK24, /* Clock 24 */
181 QE_CLK_DUMMY
182} qe_clock_e;
183
184/* QE CMXGCR register
185*/
186#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
187#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
188
189/* QE CMXUCR registers
190 */
191#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
192
193/* QE BRG configuration register
194*/
195#define QE_BRGC_ENABLE 0x00010000
196#define QE_BRGC_DIVISOR_SHIFT 1
197#define QE_BRGC_DIVISOR_MAX 0xFFF
198#define QE_BRGC_DIV16 1
199
200/* QE SDMA registers
201*/
202#define QE_SDSR_BER1 0x02000000
203#define QE_SDSR_BER2 0x01000000
204
205#define QE_SDMR_GLB_1_MSK 0x80000000
206#define QE_SDMR_ADR_SEL 0x20000000
207#define QE_SDMR_BER1_MSK 0x02000000
208#define QE_SDMR_BER2_MSK 0x01000000
209#define QE_SDMR_EB1_MSK 0x00800000
210#define QE_SDMR_ER1_MSK 0x00080000
211#define QE_SDMR_ER2_MSK 0x00040000
212#define QE_SDMR_CEN_MASK 0x0000E000
213#define QE_SDMR_SBER_1 0x00000200
214#define QE_SDMR_SBER_2 0x00000200
215#define QE_SDMR_EB1_PR_MASK 0x000000C0
216#define QE_SDMR_ER1_PR 0x00000008
217
218#define QE_SDMR_CEN_SHIFT 13
219#define QE_SDMR_EB1_PR_SHIFT 6
220
221#define QE_SDTM_MSNUM_SHIFT 24
222
223#define QE_SDEBCR_BA_MASK 0x01FFFFFF
224
225void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
226void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
227uint qe_muram_alloc(uint size, uint align);
228void *qe_muram_addr(uint offset);
229int qe_get_snum(void);
230void qe_put_snum(u8 snum);
231void qe_init(uint qe_base);
232void qe_reset(void);
233void qe_assign_page(uint snum, uint para_ram_base);
234int qe_set_brg(uint brg, uint rate);
235int qe_set_mii_clk_src(int ucc_num);
236
237#endif /* __QE_H__ */