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git01.mediatek.com / filogic / uboot / 1e081eb9702a47e48ae255c4052a609470fe8565 / . / arch / arm / dts / k3-am625-r5-sk.dts
blob: 34c501dd51bb458bd0972fbf332f26c975dfb5db [file] [log] [blame]
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM625 SK dts file for R5 SPL
4 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
7#include "k3-am625-sk.dts"
8#include "k3-am62x-sk-ddr4-1600MTs.dtsi"
9#include "k3-am62-ddr.dtsi"
10
11#include "k3-am625-sk-u-boot.dtsi"
12
13/ {
14 aliases {
Manorit Chawdhry1e081eb2024-11-21 17:32:51 +0530[diff] [blame^]15 tick-timer = &main_timer0;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]16 remoteproc0 = &sysctrler;
17 remoteproc1 = &a53_0;
18 serial0 = &wkup_uart0;
19 serial3 = &main_uart1;
20 };
21
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]22 a53_0: a53@0 {
23 compatible = "ti,am654-rproc";
24 reg = <0x00 0x00a90000 0x00 0x10>;
25 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhryf023d772023-04-14 09:47:59 +0530[diff] [blame]26 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
27 <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]28 resets = <&k3_reset 135 0>;
Manorit Chawdhryf23728b2024-10-15 16:22:19 +0530[diff] [blame]29 clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
30 clock-names = "gtc", "core";
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]31 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
32 assigned-clock-parents = <&k3_clks 61 2>;
33 assigned-clock-rates = <200000000>, <1200000000>;
34 ti,sci = <&dmsc>;
35 ti,sci-proc-id = <32>;
36 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]38 };
39
40 dm_tifs: dm-tifs {
41 compatible = "ti,j721e-dm-sci";
42 ti,host-id = <36>;
43 ti,secure-host;
44 mbox-names = "rx", "tx";
45 mboxes= <&secure_proxy_main 22>,
46 <&secure_proxy_main 23>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]48 };
49};
50
51&dmsc {
52 mboxes= <&secure_proxy_main 0>,
53 <&secure_proxy_main 1>,
54 <&secure_proxy_main 0>;
55 mbox-names = "rx", "tx", "notify";
56 ti,host-id = <35>;
57 ti,secure-host;
58};
59
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]60&secure_proxy_sa3 {
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]61 /* We require this for boot handshake */
62 status = "okay";
63};
64
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]65&cbass_main {
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]66 sysctrler: sysctrler {
67 compatible = "ti,am654-system-controller";
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]68 mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]69 mbox-names = "tx", "rx", "boot_notify";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]71 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]72};
73
Manorit Chawdhry1e081eb2024-11-21 17:32:51 +0530[diff] [blame^]74&main_timer0 {
75 /delete-property/ clocks;
76 /delete-property/ clocks-names;
77 /delete-property/ assigned-clocks;
78 /delete-property/ assigned-clock-parents;
79 clock-frequency = <25000000>;
80};
81
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]82/* WKUP UART0 is used for DM firmware logs */
83&wkup_uart0 {
Nishanth Menonb26b8cf2023-11-14 21:28:57 -0600[diff] [blame]84 status = "okay";
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]85};
86
87/* Main UART1 is used for TIFS firmware logs */
88&main_uart1 {
Nishanth Menonb26b8cf2023-11-14 21:28:57 -0600[diff] [blame]89 status = "okay";
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]90};
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]91
92&ospi0 {
93 reg = <0x00 0x0fc40000 0x00 0x100>,
94 <0x00 0x60000000 0x00 0x08000000>;
95};
Siddharth Vadapallib5e87a22024-08-26 15:55:14 +0530[diff] [blame]96
97&main_pktdma {
98 ti,sci = <&dm_tifs>;
99 bootph-all;
100};