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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier peripheral core reset in glue layer
8
9description: |
10 Some peripheral core reset belongs to its own glue layer. Before using
11 this core reset, it is necessary to control the clocks and resets to
12 enable this layer. These clocks and resets should be described in each
13 property.
14
15maintainers:
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17
18properties:
19 compatible:
20 enum:
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
25 - socionext,uniphier-pxs3-usb3-reset
26 - socionext,uniphier-nx1-usb3-reset
27 - socionext,uniphier-pro4-ahci-reset
28 - socionext,uniphier-pxs2-ahci-reset
29 - socionext,uniphier-pxs3-ahci-reset
30
31 reg:
32 maxItems: 1
33
34 "#reset-cells":
35 const: 1
36
37 clocks:
38 minItems: 1
39 maxItems: 2
40
41 clock-names: true
42
43 resets:
44 minItems: 1
45 maxItems: 2
46
47 reset-names: true
48
49allOf:
50 - if:
51 properties:
52 compatible:
53 contains:
54 enum:
55 - socionext,uniphier-pro4-usb3-reset
56 - socionext,uniphier-pro5-usb3-reset
57 - socionext,uniphier-pro4-ahci-reset
58 then:
59 properties:
60 clocks:
61 minItems: 2
62 maxItems: 2
63 clock-names:
64 items:
65 - const: gio
66 - const: link
67 resets:
68 minItems: 2
69 maxItems: 2
70 reset-names:
71 items:
72 - const: gio
73 - const: link
74 else:
75 properties:
76 clocks:
77 maxItems: 1
78 clock-names:
79 const: link
80 resets:
81 maxItems: 1
82 reset-names:
83 const: link
84
85additionalProperties: false
86
87required:
88 - compatible
89 - reg
90 - "#reset-cells"
91 - clocks
92 - clock-names
93 - resets
94 - reset-names
95
96examples:
97 - |
98 usb_rst: reset-controller@0 {
99 compatible = "socionext,uniphier-ld20-usb3-reset";
100 reg = <0x0 0x4>;
101 #reset-cells = <1>;
102 clock-names = "link";
103 clocks = <&sys_clk 14>;
104 reset-names = "link";
105 resets = <&sys_rst 14>;
106 };