| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/reset/microchip,rst.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Microchip Sparx5 Switch Reset Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Steen Hegelund <steen.hegelund@microchip.com> |
| 11 | - Lars Povlsen <lars.povlsen@microchip.com> |
| 12 | |
| 13 | description: | |
| 14 | The Microchip Sparx5 Switch provides reset control and implements the following |
| 15 | functions |
| 16 | - One Time Switch Core Reset (Soft Reset) |
| 17 | |
| 18 | properties: |
| 19 | $nodename: |
| 20 | pattern: "^reset-controller@[0-9a-f]+$" |
| 21 | |
| 22 | compatible: |
| 23 | enum: |
| 24 | - microchip,sparx5-switch-reset |
| 25 | - microchip,lan966x-switch-reset |
| 26 | |
| 27 | reg: |
| 28 | items: |
| 29 | - description: global control block registers |
| 30 | |
| 31 | reg-names: |
| 32 | items: |
| 33 | - const: gcb |
| 34 | |
| 35 | "#reset-cells": |
| 36 | const: 1 |
| 37 | |
| 38 | cpu-syscon: |
| 39 | $ref: /schemas/types.yaml#/definitions/phandle |
| 40 | description: syscon used to access CPU reset |
| 41 | |
| 42 | required: |
| 43 | - compatible |
| 44 | - reg |
| 45 | - reg-names |
| 46 | - "#reset-cells" |
| 47 | - cpu-syscon |
| 48 | |
| 49 | additionalProperties: false |
| 50 | |
| 51 | examples: |
| 52 | - | |
| 53 | reset: reset-controller@11010008 { |
| 54 | compatible = "microchip,sparx5-switch-reset"; |
| 55 | reg = <0x11010008 0x4>; |
| 56 | reg-names = "gcb"; |
| 57 | #reset-cells = <1>; |
| 58 | cpu-syscon = <&cpu_ctrl>; |
| 59 | }; |