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git01.mediatek.com / filogic / uboot / 1d9e7b89955a231fc10ff5332e7ed048d1c05cb7 / . / dts / upstream / Bindings / display / tegra / nvidia,tegra20-gr3d.yaml
blob: 59a52e732ca3f61a7b1fbf5e9fbe2e1a52a1317b [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA 3D graphics engine
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14 $nodename:
15 pattern: "^gr3d@[0-9a-f]+$"
16
17 compatible:
18 enum:
19 - nvidia,tegra20-gr3d
20 - nvidia,tegra30-gr3d
21 - nvidia,tegra114-gr3d
22
23 reg:
24 maxItems: 1
25
26 clocks:
27 minItems: 1
28 maxItems: 2
29
30 clock-names:
31 minItems: 1
32 maxItems: 2
33
34 resets:
35 minItems: 2
36 maxItems: 4
37
38 reset-names:
39 minItems: 2
40 maxItems: 4
41
42 iommus:
43 minItems: 1
44 maxItems: 2
45
46 interconnects:
47 minItems: 4
48 maxItems: 10
49
50 interconnect-names:
51 minItems: 4
52 maxItems: 10
53
54 operating-points-v2: true
55
56 power-domains:
57 minItems: 1
58 maxItems: 2
59
60 power-domain-names:
61 maxItems: 2
62
63allOf:
64 - if:
65 properties:
66 compatible:
67 contains:
68 const: nvidia,tegra20-gr2d
69 then:
70 properties:
71 clocks:
72 items:
73 - description: module clock
74
75 clock-names:
76 items:
77 - const: 3d
78
79 resets:
80 items:
81 - description: module reset
82 - description: memory client hotflush reset
83
84 reset-names:
85 items:
86 - const: 3d
87 - const: mc
88
89 iommus:
90 maxItems: 1
91
92 interconnects:
93 minItems: 4
94 maxItems: 4
95
96 interconnect-names:
97 minItems: 4
98 maxItems: 4
99
100 power-domains:
101 items:
102 - description: phandle to the TD power domain
103
104 - if:
105 properties:
106 compatible:
107 contains:
108 const: nvidia,tegra30-gr3d
109 then:
110 properties:
111 clocks:
112 items:
113 - description: primary module clock
114 - description: secondary module clock
115
116 clock-names:
117 items:
118 - const: 3d
119 - const: 3d2
120
121 resets:
122 items:
123 - description: primary module reset
124 - description: secondary module reset
125 - description: primary memory client hotflush reset
126 - description: secondary memory client hotflush reset
127
128 reset-names:
129 items:
130 - const: 3d
131 - const: 3d2
132 - const: mc
133 - const: mc2
134
135 iommus:
136 minItems: 2
137 maxItems: 2
138
139 interconnects:
140 minItems: 8
141 maxItems: 8
142
143 interconnect-names:
144 minItems: 8
145 maxItems: 8
146
147 power-domains:
148 items:
149 - description: phandle to the TD power domain
150 - description: phandle to the TD2 power domain
151
152 power-domain-names:
153 items:
154 - const: 3d0
155 - const: 3d1
156
157 dependencies:
158 power-domains: [ power-domain-names ]
159
160 - if:
161 properties:
162 compatible:
163 contains:
164 const: nvidia,tegra114-gr2d
165 then:
166 properties:
167 clocks:
168 items:
169 - description: module clock
170
171 clock-names:
172 items:
173 - const: 3d
174
175 resets:
176 items:
177 - description: module reset
178 - description: memory client hotflush reset
179
180 reset-names:
181 items:
182 - const: 3d
183 - const: mc
184
185 iommus:
186 maxItems: 1
187
188 interconnects:
189 minItems: 10
190 maxItems: 10
191
192 interconnect-names:
193 minItems: 10
194 maxItems: 10
195
196 power-domains:
197 items:
198 - description: phandle to the TD power domain
199
200additionalProperties: false
201
202examples:
203 - |
204 #include <dt-bindings/clock/tegra20-car.h>
205 #include <dt-bindings/memory/tegra20-mc.h>
206
207 gr3d@54180000 {
208 compatible = "nvidia,tegra20-gr3d";
209 reg = <0x54180000 0x00040000>;
210 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
211 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
212 reset-names = "3d", "mc";
213 };