| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | Binding for the AXS10X Generic PLL clock |
| 2 | |
| 3 | This binding uses the common clock binding[1]. |
| 4 | |
| 5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 6 | |
| 7 | Required properties: |
| 8 | - compatible: should be "snps,axs10x-<name>-pll-clock" |
| 9 | "snps,axs10x-arc-pll-clock" |
| 10 | "snps,axs10x-pgu-pll-clock" |
| 11 | - reg: should always contain 2 pairs address - length: first for PLL config |
| 12 | registers and second for corresponding LOCK CGU register. |
| 13 | - clocks: shall be the input parent clock phandle for the PLL. |
| 14 | - #clock-cells: from common clock binding; Should always be set to 0. |
| 15 | |
| 16 | Example: |
| 17 | input-clk: input-clk { |
| 18 | clock-frequency = <33333333>; |
| 19 | compatible = "fixed-clock"; |
| 20 | #clock-cells = <0>; |
| 21 | }; |
| 22 | |
| 23 | core-clk: core-clk@80 { |
| 24 | compatible = "snps,axs10x-arc-pll-clock"; |
| 25 | reg = <0x80 0x10>, <0x100 0x10>; |
| 26 | #clock-cells = <0>; |
| 27 | clocks = <&input-clk>; |
| 28 | }; |