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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shengzhou Liuf13321d2014-03-05 15:04:48 +08002/*
3 * Copyright 2014 Freescale Semiconductor
4 *
Shengzhou Liuf13321d2014-03-05 15:04:48 +08005 * Freescale T2080RDB board-specific CPLD controlling supports.
6 */
7
8#include <common.h>
9#include <command.h>
10#include "cpld.h"
11
12u8 cpld_read(unsigned int reg)
13{
Tom Rini6a5dccc2022-11-16 13:10:41 -050014 void *p = (void *)CFG_SYS_CPLD_BASE;
Shengzhou Liuf13321d2014-03-05 15:04:48 +080015
16 return in_8(p + reg);
17}
18
19void cpld_write(unsigned int reg, u8 value)
20{
Tom Rini6a5dccc2022-11-16 13:10:41 -050021 void *p = (void *)CFG_SYS_CPLD_BASE;
Shengzhou Liuf13321d2014-03-05 15:04:48 +080022
23 out_8(p + reg, value);
24}
25
26/* Set the boot bank to the alternate bank */
27void cpld_set_altbank(void)
28{
29 u8 reg = CPLD_READ(flash_csr);
30
31 reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
32 CPLD_WRITE(flash_csr, reg);
33 CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
34}
35
36/* Set the boot bank to the default bank */
37void cpld_set_defbank(void)
38{
39 u8 reg = CPLD_READ(flash_csr);
40
41 reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
42 CPLD_WRITE(flash_csr, reg);
43 CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
44}
45
Simon Glassed38aef2020-05-10 11:40:03 -060046int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
Shengzhou Liuf13321d2014-03-05 15:04:48 +080047{
48 int rc = 0;
49
50 if (argc <= 1)
51 return cmd_usage(cmdtp);
52
53 if (strcmp(argv[1], "reset") == 0) {
54 if (strcmp(argv[2], "altbank") == 0)
55 cpld_set_altbank();
56 else
57 cpld_set_defbank();
58 } else {
59 rc = cmd_usage(cmdtp);
60 }
61
62 return rc;
63}
64
65U_BOOT_CMD(
66 cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
67 "Reset the board or alternate bank",
68 "reset: reset to default bank\n"
69 "cpld reset altbank: reset to alternate bank\n"
70);