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wdenk591dda52002-11-18 00:14:45 +00001/*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef _ASM_IC_SC520_H_
25#define _ASM_IC_SC520_H_ 1
26
Graeme Russ1d977dc2009-08-23 12:59:56 +100027#ifndef __ASSEMBLY__
28
29void init_sc520(void);
30unsigned long init_sc520_dram(void);
31
32/* Memory mapped configuration registers */
33typedef struct sc520_mmcr {
34 u16 revid; /* ElanSC520 microcontroller revision id */
35 u8 cpuctl; /* am5x86 CPU control */
36
37 u8 pad_0x003[0x0d];
38
39 u8 drcctl; /* SDRAM control */
40 u8 pad_0x011[0x01];
41 u8 drctmctl; /* SDRAM timing control */
42 u8 pad_0x013[0x01];
43 u16 drccfg; /* SDRAM bank configuration*/
44 u8 pad_0x016[0x02];
45 u32 drcbendadr; /* SDRAM bank 0-3 ending address*/
46 u8 pad_0x01c[0x04];
47 u8 eccctl; /* ECC control */
48 u8 eccsta; /* ECC status */
49 u8 eccckbpos; /* ECC check bit position */
50 u8 ecccktest; /* ECC Check Code Test */
51 u32 eccsbadd; /* ECC single-bit error address */
52 u32 eccmbadd; /* ECC multi-bit error address */
53
54 u8 pad_0x02c[0x14];
55
56 u8 dbctl; /* SDRAM buffer control */
57
58 u8 pad_0x041[0x0f];
59
60 u16 bootcsctl; /* /BOOTCS control */
61 u8 pad_0x052[0x02];
62 u16 romcs1ctl; /* /ROMCS1 control */
63 u16 romcs2ctl; /* /ROMCS2 control */
64
65 u8 pad_0x058[0x08];
66
67 u16 hbctl; /* host bridge control */
68 u16 hbtgtirqctl; /* host bridge target interrupt control */
69 u16 hbtgtirqsta; /* host bridge target interrupt status */
70 u16 hbmstirqctl; /* host bridge target interrupt control */
71 u16 hbmstirqsta; /* host bridge master interrupt status */
72 u8 pad_0x06a[0x02];
73 u32 mstintadd; /* host bridge master interrupt address */
74
75 u8 sysarbctl; /* system arbiter control */
76 u8 pciarbsta; /* PCI bus arbiter status */
77 u16 sysarbmenb; /* system arbiter master enable */
78 u32 arbprictl; /* arbiter priority control */
79
80 u8 pad_0x078[0x08];
81
82 u8 adddecctl; /* address decode control */
83 u8 pad_0x081[0x01];
84 u16 wpvsta; /* write-protect violation status */
85 u8 pad_0x084[0x04];
86 u32 par[16]; /* programmable address regions */
87
88 u8 pad_0x0c8[0x0b38];
89
90 u8 gpecho; /* GP echo mode */
91 u8 gpcsdw; /* GP chip select data width */
92 u16 gpcsqual; /* GP chip select qualification */
93 u8 pad_0xc04[0x4];
94 u8 gpcsrt; /* GP chip select recovery time */
95 u8 gpcspw; /* GP chip select pulse width */
96 u8 gpcsoff; /* GP chip select offset */
97 u8 gprdw; /* GP read pulse width */
98 u8 gprdoff; /* GP read offset */
99 u8 gpwrw; /* GP write pulse width */
100 u8 gpwroff; /* GP write offset */
101 u8 gpalew; /* GP ale pulse width */
102 u8 gpaleoff; /* GP ale offset */
103
104 u8 pad_0xc11[0x0f];
105
106 u16 piopfs15_0; /* PIO15-PIO0 pin function select */
107 u16 piopfs31_16; /* PIO31-PIO16 pin function select */
108 u8 cspfs; /* chip select pin function select */
109 u8 pad_0xc25[0x01];
110 u8 clksel; /* clock select */
111 u8 pad_0xc27[0x01];
112 u16 dsctl; /* drive strength control */
113 u16 piodir15_0; /* PIO15-PIO0 direction */
114 u16 piodir31_16; /* PIO31-PIO16 direction */
115 u8 pad_0xc2e[0x02];
116 u16 piodata15_0 ; /* PIO15-PIO0 data */
117 u16 piodata31_16; /* PIO31-PIO16 data */
118 u16 pioset15_0; /* PIO15-PIO0 set */
119 u16 pioset31_16; /* PIO31-PIO16 set */
120 u16 pioclr15_0; /* PIO15-PIO0 clear */
121 u16 pioclr31_16; /* PIO31-PIO16 clear */
122
123 u8 pad_0xc3c[0x24];
124
125 u16 swtmrmilli; /* software timer millisecond count */
126 u16 swtmrmicro; /* software timer microsecond count */
127 u8 swtmrcfg; /* software timer configuration */
128
129 u8 pad_0xc65[0x0b];
130
131 u8 gptmrsta; /* GP timers status register */
132 u8 pad_0xc71;
133 u16 gptmr0ctl; /* GP timer 0 mode/control */
134 u16 gptmr0cnt; /* GP timer 0 count */
135 u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */
136 u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */
137 u16 gptmr1ctl; /* GP timer 1 mode/control */
138 u16 gptmr1cnt; /* GP timer 1 count */
139 u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */
140 u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/
141 u16 gptmr2ctl; /* GP timer 2 mode/control */
142 u16 gptmr2cnt; /* GP timer 2 count */
143 u8 pad_0xc86[0x08];
144 u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */
145
146 u8 pad_0xc90[0x20];
147
148 u16 wdtmrctl; /* watchdog timer control */
149 u16 wdtmrcntl; /* watchdog timer count low */
150 u16 wdtmrcnth; /* watchdog timer count high */
151
152 u8 pad_0xcb6[0x0a];
153
154 u8 uart1ctl; /* UART 1 general control */
155 u8 uart1sta; /* UART 1 general status */
156 u8 uart1fcrshad; /* UART 1 FIFO control shadow */
157 u8 pad_0xcc3[0x01];
158 u8 uart2ctl; /* UART 2 general control */
159 u8 uart2sta; /* UART 2 general status */
160 u8 uart2fcrshad; /* UART 2 FIFO control shadow */
161
162 u8 pad_0xcc7[0x09];
163
164 u8 ssictl; /* SSI control */
165 u8 ssixmit; /* SSI transmit */
166 u8 ssicmd; /* SSI command */
167 u8 ssista; /* SSI status */
168 u8 ssircv; /* SSI receive */
169
170 u8 pad_0xcd5[0x2b];
171
172 u8 picicr; /* interrupt control */
173 u8 pad_0xd01[0x01];
174 u8 pic_mode[3]; /* PIC interrupt mode */
175 u8 pad_0xd05[0x03];
176 u16 swint16_1; /* software interrupt 16-1 control */
177 u8 swint22_17; /* software interrupt 22-17/NMI control */
178 u8 pad_0xd0b[0x05];
179 u16 intpinpol; /* interrupt pin polarity */
180 u8 pad_0xd12[0x02];
181 u16 pcihostmap; /* PCI host bridge interrupt mapping */
182 u8 pad_0xd16[0x02];
183 u16 eccmap; /* ECC interrupt mapping */
184 u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */
185 u8 pad_0xd1d[0x03];
186 u8 pit_int_map[3]; /* PIT interrupt mapping */
187 u8 pad_0xd23[0x05];
188 u8 uart_int_map[2]; /* UART interrupt mapping */
189 u8 pad_0xd2a[0x06];
190 u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/
191 u8 pad_0xd34[0x0c];
192 u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */
193 u8 ssimap; /* SSI interrupt mapping register */
194 u8 wdtmap; /* watchdog timer interrupt mapping */
195 u8 rtcmap; /* RTC interrupt mapping register */
196 u8 wpvmap; /* write-protect interrupt mapping */
197 u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */
198 u8 ferrmap; /* floating point error interrupt mapping */
199 u8 pad_0xd47[0x09];
200 u8 gp_int_map[11]; /* GP IRQ interrupt mapping */
201
202 u8 pad_0xd5b[0x15];
203
204 u8 sysinfo; /* system board information */
205 u8 pad_0xd71[0x01];
206 u8 rescfg; /* reset configuration */
207 u8 pad_0xd73[0x01];
208 u8 ressta; /* reset status */
209
210 u8 pad_0xd75[0x0b];
211
212 u8 gpdmactl; /* GP-DMA Control */
213 u8 gpdmammio; /* GP-DMA memory-mapped I/O */
214 u16 gpdmaextchmapa; /* GP-DMA resource channel map a */
215 u16 gpdmaextchmapb; /* GP-DMA resource channel map b */
216 u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */
217 u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */
218 u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */
219 u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */
220 u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */
221 u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */
222 u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */
223 u8 pad_0xd8d[0x03];
224 u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */
225 u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */
226 u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */
227 u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */
228 u8 pad_0xd94[0x4];
229 u8 gpdmabcctl; /* buffer chaining control */
230 u8 gpdmabcsta; /* buffer chaining status */
231 u8 gpdmabsintenb; /* buffer chaining interrupt enable */
232 u8 gpdmabcval; /* buffer chaining valid */
233 u8 pad_0xd9c[0x04];
234 u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */
235 u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */
236 u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */
237 u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */
238 u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */
239 u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */
240 u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */
241 u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */
242 u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */
243 u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */
244 u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */
245 u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */
246 u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */
247 u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */
248 u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */
249 u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */
250
251 u8 pad_0xdc0[0x0240];
252} sc520_mmcr_t;
253
254extern volatile sc520_mmcr_t *sc520_mmcr;
255
256#endif
257
258/* MMCR Offsets (required for assembler code */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200259#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200260#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */
261#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */
Graeme Russ1d977dc2009-08-23 12:59:56 +1000262#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */
263#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */
wdenk591dda52002-11-18 00:14:45 +0000264
265/* MMCR Register bits (not all of them :) ) */
266
wdenkabda5ca2003-05-31 18:35:21 +0000267/* SSI Stuff */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200268#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */
269#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */
270#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */
271#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */
272#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */
273#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */
274#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */
275#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */
wdenkabda5ca2003-05-31 18:35:21 +0000276
Wolfgang Denka1be4762008-05-20 16:00:29 +0200277#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */
278#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */
279#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */
280#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */
wdenkabda5ca2003-05-31 18:35:21 +0000281
Wolfgang Denka1be4762008-05-20 16:00:29 +0200282#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */
283#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */
284#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */
285#define SSISTA_BSY 0x02 /* SSI Busy */
286#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */
wdenkabda5ca2003-05-31 18:35:21 +0000287
wdenk591dda52002-11-18 00:14:45 +0000288/* BITS for SC520_ADDDECCTL: */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200289#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */
290#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */
291#define RTC_DIS 0x04 /* RTC Disable */
292#define UART2_DIS 0x02 /* UART2 Disable */
293#define UART1_DIS 0x01 /* UART1 Disable */
wdenk591dda52002-11-18 00:14:45 +0000294
295/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */
wdenk57b2d802003-06-27 21:31:46 +0000296#define SC520_REG_ADDR 0x00000cf8
wdenk591dda52002-11-18 00:14:45 +0000297#define SC520_REG_DATA 0x00000cfc
298
wdenk591dda52002-11-18 00:14:45 +0000299#define SC520_ISA_MEM_PHYS 0x00000000
300#define SC520_ISA_MEM_BUS 0x00000000
301#define SC520_ISA_MEM_SIZE 0x01000000
302
303#define SC520_ISA_IO_PHYS 0x00000000
304#define SC520_ISA_IO_BUS 0x00000000
305#define SC520_ISA_IO_SIZE 0x00001000
306
wdenk57b2d802003-06-27 21:31:46 +0000307/* PCI I/O space from 0x1000 to 0xdfff
wdenkabda5ca2003-05-31 18:35:21 +0000308 * (make 0xe000-0xfdff available for stuff like PCCard boot) */
wdenk591dda52002-11-18 00:14:45 +0000309#define SC520_PCI_IO_PHYS 0x00001000
310#define SC520_PCI_IO_BUS 0x00001000
wdenkabda5ca2003-05-31 18:35:21 +0000311#define SC520_PCI_IO_SIZE 0x0000d000
wdenk591dda52002-11-18 00:14:45 +0000312
313/* system memory from 0x00000000 to 0x0fffffff */
314#define SC520_PCI_MEMORY_PHYS 0x00000000
315#define SC520_PCI_MEMORY_BUS 0x00000000
316#define SC520_PCI_MEMORY_SIZE 0x10000000
317
wdenk57b2d802003-06-27 21:31:46 +0000318/* PCI bus memory from 0x10000000 to 0x26ffffff
wdenkabda5ca2003-05-31 18:35:21 +0000319 * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
wdenk591dda52002-11-18 00:14:45 +0000320#define SC520_PCI_MEM_PHYS 0x10000000
Wolfgang Denka1be4762008-05-20 16:00:29 +0200321#define SC520_PCI_MEM_BUS 0x10000000
wdenkabda5ca2003-05-31 18:35:21 +0000322#define SC520_PCI_MEM_SIZE 0x17000000
wdenk591dda52002-11-18 00:14:45 +0000323
324/* 0x28000000 - 0x3fffffff is used by the flash banks */
325
326/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
327
wdenkabda5ca2003-05-31 18:35:21 +0000328/* priority numbers used for interrupt channel mappings */
329#define SC520_IRQ_DISABLED 0
330#define SC520_IRQ0 1
331#define SC520_IRQ1 2
332#define SC520_IRQ2 4 /* same as IRQ9 */
333#define SC520_IRQ3 11
334#define SC520_IRQ4 12
335#define SC520_IRQ5 13
336#define SC520_IRQ6 21
337#define SC520_IRQ7 22
338#define SC520_IRQ8 3
339#define SC520_IRQ9 4
wdenk57b2d802003-06-27 21:31:46 +0000340#define SC520_IRQ10 5
wdenkabda5ca2003-05-31 18:35:21 +0000341#define SC520_IRQ11 6
342#define SC520_IRQ12 7
343#define SC520_IRQ13 8
344#define SC520_IRQ14 9
345#define SC520_IRQ15 10
346
wdenk591dda52002-11-18 00:14:45 +0000347#endif