Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | abf7a7c | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 2 | /* |
wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 3 | * (C) Copyright 2002 |
wdenk | abf7a7c | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
wdenk | abf7a7c | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame^] | 8 | #include <cpu_func.h> |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 9 | #include <asm/immap.h> |
| 10 | #include <asm/cache.h> |
wdenk | abf7a7c | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 11 | |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 12 | volatile int *cf_icache_status = (int *)ICACHE_STATUS; |
| 13 | volatile int *cf_dcache_status = (int *)DCACHE_STATUS; |
| 14 | |
| 15 | void flush_cache(ulong start_addr, ulong size) |
wdenk | abf7a7c | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 16 | { |
wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 17 | /* Must be implemented for all M68k processors with copy-back data cache */ |
wdenk | abf7a7c | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 18 | } |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 19 | |
| 20 | int icache_status(void) |
| 21 | { |
| 22 | return *cf_icache_status; |
| 23 | } |
| 24 | |
| 25 | int dcache_status(void) |
| 26 | { |
| 27 | return *cf_dcache_status; |
| 28 | } |
| 29 | |
| 30 | void icache_enable(void) |
| 31 | { |
| 32 | icache_invalid(); |
| 33 | |
| 34 | *cf_icache_status = 1; |
| 35 | |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 36 | #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 37 | __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2)); |
| 38 | __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3)); |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 39 | #if defined(CONFIG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 40 | __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6)); |
| 41 | __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7)); |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 42 | #endif |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 43 | #else |
| 44 | __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); |
| 45 | __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); |
| 46 | #endif |
| 47 | |
| 48 | __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR)); |
| 49 | } |
| 50 | |
| 51 | void icache_disable(void) |
| 52 | { |
| 53 | u32 temp = 0; |
| 54 | |
| 55 | *cf_icache_status = 0; |
| 56 | icache_invalid(); |
| 57 | |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 58 | #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 59 | __asm__ __volatile__("movec %0, %%acr2"::"r"(temp)); |
| 60 | __asm__ __volatile__("movec %0, %%acr3"::"r"(temp)); |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 61 | #if defined(CONFIG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 62 | __asm__ __volatile__("movec %0, %%acr6"::"r"(temp)); |
| 63 | __asm__ __volatile__("movec %0, %%acr7"::"r"(temp)); |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 64 | #endif |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 65 | #else |
| 66 | __asm__ __volatile__("movec %0, %%acr0"::"r"(temp)); |
| 67 | __asm__ __volatile__("movec %0, %%acr1"::"r"(temp)); |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 68 | #endif |
| 69 | } |
| 70 | |
| 71 | void icache_invalid(void) |
| 72 | { |
| 73 | u32 temp; |
| 74 | |
| 75 | temp = CONFIG_SYS_ICACHE_INV; |
| 76 | if (*cf_icache_status) |
| 77 | temp |= CONFIG_SYS_CACHE_ICACR; |
| 78 | |
| 79 | __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); |
| 80 | } |
| 81 | |
| 82 | /* |
| 83 | * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x |
| 84 | * the dcache will be dummy in ColdFire V2 and V3 |
| 85 | */ |
| 86 | void dcache_enable(void) |
| 87 | { |
| 88 | dcache_invalid(); |
| 89 | *cf_dcache_status = 1; |
| 90 | |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 91 | #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 92 | __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); |
| 93 | __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 94 | #if defined(CONFIG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 95 | __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4)); |
| 96 | __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5)); |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 97 | #endif |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 98 | #endif |
| 99 | |
| 100 | __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR)); |
| 101 | } |
| 102 | |
| 103 | void dcache_disable(void) |
| 104 | { |
| 105 | u32 temp = 0; |
| 106 | |
| 107 | *cf_dcache_status = 0; |
| 108 | dcache_invalid(); |
| 109 | |
| 110 | __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); |
| 111 | |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 112 | #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 113 | __asm__ __volatile__("movec %0, %%acr0"::"r"(temp)); |
| 114 | __asm__ __volatile__("movec %0, %%acr1"::"r"(temp)); |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 115 | #if defined(CONFIG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 116 | __asm__ __volatile__("movec %0, %%acr4"::"r"(temp)); |
| 117 | __asm__ __volatile__("movec %0, %%acr5"::"r"(temp)); |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 118 | #endif |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 119 | #endif |
| 120 | } |
| 121 | |
| 122 | void dcache_invalid(void) |
| 123 | { |
Angelo Dureghello | 8ddcf38 | 2017-05-31 21:32:48 +0200 | [diff] [blame] | 124 | #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 125 | u32 temp; |
| 126 | |
| 127 | temp = CONFIG_SYS_DCACHE_INV; |
| 128 | if (*cf_dcache_status) |
| 129 | temp |= CONFIG_SYS_CACHE_DCACR; |
| 130 | if (*cf_icache_status) |
| 131 | temp |= CONFIG_SYS_CACHE_ICACR; |
| 132 | |
| 133 | __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); |
| 134 | #endif |
| 135 | } |
Wu, Josh | 22f483c | 2015-07-27 11:40:15 +0800 | [diff] [blame] | 136 | |
| 137 | __weak void invalidate_dcache_range(unsigned long start, unsigned long stop) |
| 138 | { |
| 139 | /* An empty stub, real implementation should be in platform code */ |
| 140 | } |
| 141 | __weak void flush_dcache_range(unsigned long start, unsigned long stop) |
| 142 | { |
| 143 | /* An empty stub, real implementation should be in platform code */ |
| 144 | } |