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git01.mediatek.com / filogic / uboot / 1d8bbff36546baffa5062a7090a465448e527adf / . / arch / arm / dts / k3-am65-iot2050-common-u-boot.dtsi
blob: 082a3c89d0fd7e416e4bbbc6166c50d4067d4e3d [file] [log] [blame]
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Jan Kiszka423a98b2022-02-16 09:06:49 +0100[diff] [blame]3 * Copyright (c) Siemens AG, 2018-2022
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]4 *
5 * Authors:
6 * Le Jin <le.jin@siemens.com>
7 * Jan Kiszka <jan.kiszka@siemens.com>
8 *
9 * Common U-Boot bits of the IOT2050 Basic and Advanced variants
10 */
11
12/ {
13 aliases {
14 spi0 = &ospi0;
15 };
16
17 leds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]19 status-led-red {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]21 };
22 status-led-green {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]24 };
25 };
26};
27
28&cbass_mcu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Jan Kiszka423a98b2022-02-16 09:06:49 +0100[diff] [blame]30
31 mcu_navss: bus@28380000 {
32 ringacc@2b800000 {
33 reg = <0x0 0x2b800000 0x0 0x400000>,
34 <0x0 0x2b000000 0x0 0x400000>,
35 <0x0 0x28590000 0x0 0x100>,
36 <0x0 0x2a500000 0x0 0x40000>,
37 <0x0 0x28440000 0x0 0x40000>;
38 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
39 ti,dma-ring-reset-quirk;
40 };
41
42 dma-controller@285c0000 {
43 reg = <0x0 0x285c0000 0x0 0x100>,
44 <0x0 0x284c0000 0x0 0x4000>,
45 <0x0 0x2a800000 0x0 0x40000>,
46 <0x0 0x284a0000 0x0 0x4000>,
47 <0x0 0x2aa00000 0x0 0x40000>,
48 <0x0 0x28400000 0x0 0x2000>;
49 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
50 "tchanrt", "rflow";
51 };
52 };
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]53};
54
55&cbass_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]57};
58
59&cbass_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Jan Kiszka24fbe6b2021-10-05 12:04:49 +0200[diff] [blame]61 main_navss: bus@30800000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]63 };
64};
65
66&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]68 mcu-fss0-ospi0-pins-default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]70 };
71};
72
73&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]75 main-uart1-pins-default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]77 };
78};
79
80&main_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]82 current-speed = <115200>;
83};
84
85&wkup_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]87};
88
89&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]91 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]93 };
94};
95
96&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]98};
99
100&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]102 k3_sysreset: sysreset-controller {
103 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]105 };
106};
107
108&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]110};
111
112&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]114};
115
116&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]118};
119
120&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Jan Kiszka4a88eb22021-09-18 08:17:52 +0200[diff] [blame]122};