Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 1d8bbff36546baffa5062a7090a465448e527adf / . / arch / arm / dts / imx8mm-verdin-dev.dtsi
blob: 3c4b8ca125e3211b172b2656301e02ebbee5b0f1 [file] [log] [blame]
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]6/ {
7 sound_card: sound-card {
8 compatible = "simple-audio-card";
9 simple-audio-card,bitclock-master = <&dailink_master>;
10 simple-audio-card,format = "i2s";
11 simple-audio-card,frame-master = <&dailink_master>;
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]12 simple-audio-card,mclk-fs = <256>;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]13 simple-audio-card,name = "imx8mm-nau8822";
14 simple-audio-card,routing =
15 "Headphones", "LHP",
16 "Headphones", "RHP",
17 "Speaker", "LSPK",
18 "Speaker", "RSPK",
19 "Line Out", "AUXOUT1",
20 "Line Out", "AUXOUT2",
21 "LAUX", "Line In",
22 "RAUX", "Line In",
23 "LMICP", "Mic In",
24 "RMICP", "Mic In";
25 simple-audio-card,widgets =
26 "Headphones", "Headphones",
27 "Line Out", "Line Out",
28 "Speaker", "Speaker",
29 "Microphone", "Mic In",
30 "Line", "Line In";
31
32 dailink_master: simple-audio-card,codec {
33 clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
34 sound-dai = <&nau8822_1a>;
35 };
36
37 simple-audio-card,cpu {
38 sound-dai = <&sai2>;
39 };
40 };
41};
42
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]43/* Verdin SPI_1 */
44&ecspi2 {
45 status = "okay";
46};
47
48/* EEPROM on display adapter boards */
49&eeprom_display_adapter {
50 status = "okay";
51};
52
53/* EEPROM on Verdin Development board */
54&eeprom_carrier_board {
55 status = "okay";
56};
57
58&fec1 {
59 status = "okay";
60};
61
62/* Verdin QSPI_1 */
63&flexspi {
64 status = "okay";
65};
66
67/* Current measurement into module VCC */
68&hwmon {
69 status = "okay";
70};
71
72&hwmon_temp {
73 vs-supply = <&reg_1p8v>;
74 status = "okay";
75};
76
77&i2c3 {
78 status = "okay";
79};
80
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]81&gpio_expander_21 {
82 status = "okay";
83};
84
85/* Verdin I2C_1 */
86&i2c4 {
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]87 status = "okay";
88
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]89 /* Audio Codec */
90 nau8822_1a: audio-codec@1a {
91 compatible = "nuvoton,nau8822";
92 reg = <0x1a>;
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]93 #sound-dai-cells = <0>;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]94 };
95};
96
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]97/* Verdin PCIE_1 */
98&pcie0 {
99 status = "okay";
100};
101
102&pcie_phy {
103 status = "okay";
104};
105
106/* Verdin PWM_3_DSI */
107&pwm1 {
108 status = "okay";
109};
110
111/* Verdin PWM_1 */
112&pwm2 {
113 status = "okay";
114};
115
116/* Verdin PWM_2 */
117&pwm3 {
118 status = "okay";
119};
120
121/* Verdin I2S_1 */
122&sai2 {
123 status = "okay";
124};
125
126/* Verdin UART_3 */
127&uart1 {
128 status = "okay";
129};
130
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]131/* Verdin UART_1, connector X50 through RS485 transceiver */
132&uart2 {
133 linux,rs485-enabled-at-boot-time;
134 rs485-rts-active-low;
135 rs485-rx-during-tx;
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]136 status = "okay";
137};
138
139/* Verdin UART_2 */
140&uart3 {
141 status = "okay";
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]142};
143
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]144/* Verdin USB_1 */
145&usbotg1 {
146 disable-over-current;
147 status = "okay";
148};
149
150/* Verdin USB_2 */
151&usbotg2 {
152 disable-over-current;
153 status = "okay";
154};
155
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]156/* Limit frequency on dev board due to long traces and bad signal integrity */
157&usdhc2 {
158 max-frequency = <100000000>;
Marcel Ziswilerd86daab2023-07-11 11:09:14 +0200[diff] [blame]159 status = "okay";
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]160};