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git01.mediatek.com / filogic / uboot / 1d8bbff36546baffa5062a7090a465448e527adf / . / arch / arm / dts / imx8mm-cl-iot-gate-optee-u-boot.dtsi
blob: d93e1cbd8a7153b1f8c16949268ccda90f275ab8 [file] [log] [blame]
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Marcel Ziswiler9888e122021-10-23 01:15:12 +0200[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]8/ {
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]9 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]15
16 wdt-reboot {
17 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]19 wdt = <&wdog1>;
20 };
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]21};
22
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]23&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]25};
26
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]27&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]29};
30
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]31&binman_fip {
32 arch = "arm64";
33 compression = "none";
34 description = "Trusted Firmware FIP";
35 load = <0x40310000>;
36 type = "firmware";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]37
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]38 fip_blob {
39 filename = "fip.bin";
40 type = "blob-ext";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]41 };
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]42};
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]43
Simon Glassceea7842023-08-23 19:18:01 -0600[diff] [blame]44/* This cannot work since it refers to a template node
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200[diff] [blame]45&binman_configuration {
46 loadables = "atf", "fip";
Fabio Estevamc1e26342021-08-23 21:11:09 -0300[diff] [blame]47};
Simon Glassceea7842023-08-23 19:18:01 -0600[diff] [blame]48*/
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]49
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]50&fec1 {
51 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
52};
53
54&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]56};
57
58&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]60};
61
62&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]64};
65
66&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]68};
69
70&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]72};
73
74&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]76};
77
78&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]80};
81
82&pinctrl_i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]84};
85
86&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]88};
89
90&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]92};
93
94&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]96};
97
98&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]100};
101
102&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]104};
105
106&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]108};
109
110&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]112};
113
114&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]116};
117
118&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]120};
121
122&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]124};