Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 1d6464168dd592b2766769122cbbc63c832e9dbd / . / include / configs / sama5d3_xplained.h
blob: 1113214bcff5d3cfc82ccda57020b911c7c2ccdc [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]2/*
3 * Configuration settings for the SAMA5D3 Xplained board.
4 *
5 * Copyright (C) 2014 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Fabien Lehoussel04df71a2020-02-24 16:45:31 +0100[diff] [blame]12#include <linux/sizes.h>
Wu, Josh42587542015-03-30 14:51:19 +0800[diff] [blame]13#include "at91-sama5_common.h"
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]14
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]15/*
16 * This needs to be defined for the OHCI code to work but it is defined as
17 * ATMEL_ID_UHPHS in the CPU specific header files.
18 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]19#define ATMEL_ID_UHP 32
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]20
21/*
22 * Specify the clock enable bit in the PMC_SCER register.
23 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]24#define ATMEL_PMC_UHP (1 << 6)
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]25
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]26/* SDRAM */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]27#define CONFIG_SYS_SDRAM_BASE 0x20000000
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]28#define CONFIG_SYS_SDRAM_SIZE 0x10000000
29
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]30#ifdef CONFIG_SPL_BUILD
Wenyou Yang9ddd6fc2017-04-14 08:51:45 +0800[diff] [blame]31#define CONFIG_SYS_INIT_SP_ADDR 0x318000
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]32#else
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]33#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang9ddd6fc2017-04-14 08:51:45 +0800[diff] [blame]34 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]35#endif
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]36
37/* NAND flash */
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]38#ifdef CONFIG_CMD_NAND
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]39#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]40#define CONFIG_SYS_NAND_BASE 0x60000000
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]41/* our ALE is AD21 */
42#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
43/* our CLE is AD22 */
44#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
45#define CONFIG_SYS_NAND_ONFI_DETECTION
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]46#endif
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]47
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]48/* USB */
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]49#ifdef CONFIG_CMD_USB
50#define CONFIG_USB_ATMEL
51#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
52#define CONFIG_USB_OHCI_NEW
53#define CONFIG_SYS_USB_OHCI_CPU_INIT
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]54#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]55#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
56#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]57#endif
58
Bo Shen06ce3f42014-02-09 15:52:39 +0800[diff] [blame]59#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
60
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]61/* SPL */
Wenyou Yang9ddd6fc2017-04-14 08:51:45 +0800[diff] [blame]62#define CONFIG_SPL_MAX_SIZE 0x18000
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]63#define CONFIG_SPL_BSS_START_ADDR 0x20000000
64#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
65#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
66#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
67
Fabien Lehoussel04df71a2020-02-24 16:45:31 +0100[diff] [blame]68/* size of u-boot.bin to load */
69#define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K)
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]70
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]71#ifdef CONFIG_SD_BOOT
Guillaume GARDET602a16c2014-10-15 17:53:11 +0200[diff] [blame]72#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Wenyou Yange035ea72017-09-14 11:07:44 +0800[diff] [blame]73#endif
Bo Shen735ef1a2014-03-19 14:48:45 +0800[diff] [blame]74#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
75#define CONFIG_SYS_NAND_5_ADDR_CYCLE
76#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
77#define CONFIG_SYS_NAND_PAGE_COUNT 64
78#define CONFIG_SYS_NAND_OOBSIZE 64
79#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
80#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
81
82#endif