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git01.mediatek.com / filogic / uboot / 1d589e3518bbed70a504b8768cf830e6a271657c / . / board / cogent / mb.h
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wdenk1d589e32001-01-20 01:23:52 +0000[diff] [blame^]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * defines for Cogent Motherboards
26 */
27
28#ifndef _COGENT_MB_H
29#define _COGENT_MB_H
30
31/*
32 * Cogent Motherboard Address Map
33 *
34 * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits).
35 *
36 * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following
37 * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and
38 * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3).
39 * Most other motherboard devices have registers mapped into the area
40 * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF
41 * is free for whatever.
42 *
43 * The location of the motherboard address space in the physical address space
44 * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu
45 * module plugged into the motherboard and is configured above.
46 *
47 * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF)
48 * generally only use byte lane 0 (D0-7) for their transfers, i.e. only
49 * 8 bit, or 1 byte, transfers can take place, so all the registers are
50 * only 8 bits wide. The exceptions are the motherboard flash, which uses
51 * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space.
52 *
53 * I/O registers within the mapped motherboard devices are 64 bit aligned
54 * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
55 * will be at byte 7 (the address + 7). For little endian addressing, the
56 * register will be at byte 0 (the address + 0). To learn the endianess
57 * we must include <asm/byteorder.h>
58 *
59 * Take the CMA102 and CMA111 motherboards as examples...
60 *
61 * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3
62 * CMABus slots are each mapped directly onto the three general I/O slots.
63 *
64 * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI
65 * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard
66 * PCI Bus space is mapped onto general I/O slot 2, with a small area at the
67 * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF).
68 * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area
69 * 0xA000000-0xDFFFFFF.
70 */
71
72#define CMA_MB_RAM_BASE (CFG_CMA_MB_BASE+0x0000000)
73#define CMA_MB_RAM_SIZE 0x2000000 /* dip sws set actual size */
74
75#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
76#define CMA_MB_SLOT1_BASE (CFG_CMA_MB_BASE+0x2000000)
77#define CMA_MB_SLOT1_SIZE 0x2000000
78#endif
79
80#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
81#define CMA_MB_SLOT2_BASE (CFG_CMA_MB_BASE+0x4000000)
82#define CMA_MB_SLOT2_SIZE 0x2000000
83#endif
84#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
85#define CMA_MB_STDPCI_BASE (CFG_CMA_MB_BASE+0x4000000)
86#define CMA_MB_STDPCI_SIZE 0x1ff0000
87#define CMA_MB_V360EPC_BASE (CFG_CMA_MB_BASE+0x5ff0000)
88#define CMA_MB_V360EPC_SIZE 0x10000
89#endif
90
91#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
92#define CMA_MB_SLOT3_BASE (CFG_CMA_MB_BASE+0x6000000)
93#define CMA_MB_SLOT3_SIZE 0x2000000
94#endif
95
96#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
97#define CMA_MB_EXTPCI_BASE (CFG_CMA_MB_BASE+0xa000000)
98#define CMA_MB_EXTPCI_SIZE 0x4000000
99#endif
100
101#define CMA_MB_ROMLOW_BASE (CFG_CMA_MB_BASE+0xe000000)
102#define CMA_MB_ROMLOW_SIZE 0x800000
103#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
104#define CMA_MB_FLLOW_EXEC_BASE (CFG_CMA_MB_BASE+0xe000000)
105#define CMA_MB_FLLOW_EXEC_SIZE 0x100000
106#define CMA_MB_FLLOW_RDWR_BASE (CFG_CMA_MB_BASE+0xe400000)
107#define CMA_MB_FLLOW_RDWR_SIZE 0x400000
108#endif
109
110#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
111#define CMA_MB_RTC_BASE (CFG_CMA_MB_BASE+0xe800000)
112#define CMA_MB_RTC_SIZE 0x4000
113#endif
114
115#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
116#define CMA_MB_SERPAR_BASE (CFG_CMA_MB_BASE+0xe900000)
117#define CMA_MB_SERIALB_BASE (CMA_MB_SERPAR_BASE+0x00)
118#define CMA_MB_SERIALA_BASE (CMA_MB_SERPAR_BASE+0x40)
119#define CMA_MB_PARALLEL_BASE (CMA_MB_SERPAR_BASE+0x80)
120#define CMA_MB_SERPAR_SIZE 0xa0
121#endif
122
123#if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
124#define CMA_MB_PKBM_BASE (CFG_CMA_MB_BASE+0xe900100)
125#define CMA_MB_PKBM_SIZE 0x10
126#endif
127
128#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
129#define CMA_MB_LCD_BASE (CFG_CMA_MB_BASE+0xeb00000)
130#define CMA_MB_LCD_SIZE 0x10
131#endif
132
133#define CMA_MB_DIPSW_BASE (CFG_CMA_MB_BASE+0xec00000)
134#define CMA_MB_DIPSW_SIZE 0x10
135
136#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
137#define CMA_MB_SLOT1CFG_BASE (CFG_CMA_MB_BASE+0xf100000)
138#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
139#define CMA_MB_SER2_BASE (CMA_MB_SLOT1CFG_BASE+0x80)
140#define CMA_MB_SER2B_BASE (CMA_MB_SER2_BASE+0x00)
141#define CMA_MB_SER2A_BASE (CMA_MB_SER2_BASE+0x40)
142#endif
143#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1)
144#define CMA_MB_S1KBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
145#endif
146#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150)
147#define CMA_MB_IREQ1STAT_BASE (CMA_MB_SLOT1CFG_BASE+0x100)
148#define CMA_MB_AKBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
149#define CMA_MB_IREQ1MASK_BASE (CMA_MB_SLOT1CFG_BASE+0x300)
150#endif
151#define CMA_MB_SLOT1CFG_SIZE 0x400
152#endif
153
154#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
155#define CMA_MB_SLOT2CFG_BASE (CFG_CMA_MB_BASE+0xf200000)
156#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
157#define CMA_MB_S2KBM_BASE (CMA_MB_SLOT2CFG_BASE+0x200)
158#endif
159#define CMA_MB_SLOT2CFG_SIZE 0x400
160#endif
161
162#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
163#define CMA_MB_PCICTL_BASE (CFG_CMA_MB_BASE+0xf200000)
164#define CMA_MB_PCI_V3CTL_BASE (CMA_MB_PCICTL_BASE+0x100)
165#define CMA_MB_PCI_IDSEL_BASE (CMA_MB_PCICTL_BASE+0x200)
166#define CMA_MB_PCI_IMASK_BASE (CMA_MB_PCICTL_BASE+0x300)
167#define CMA_MB_PCI_ISTAT_BASE (CMA_MB_PCICTL_BASE+0x400)
168#define CMA_MB_PCI_MBID_BASE (CMA_MB_PCICTL_BASE+0x500)
169#define CMA_MB_PCI_MBREV_BASE (CMA_MB_PCICTL_BASE+0x600)
170#define CMA_MB_PCICTL_SIZE 0x700
171#endif
172
173#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
174#define CMA_MB_SLOT3CFG_BASE (CFG_CMA_MB_BASE+0xf300000)
175#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
176#define CMA_MB_S3KBM_BASE (CMA_MB_SLOT3CFG_BASE+0x200)
177#endif
178#define CMA_MB_SLOT3CFG_SIZE 0x400
179#endif
180
181#define CMA_MB_ROMHIGH_BASE (CFG_CMA_MB_BASE+0xf800000)
182#define CMA_MB_ROMHIGH_SIZE 0x800000
183#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
184#define CMA_MB_FLHIGH_EXEC_BASE (CFG_CMA_MB_BASE+0xf800000)
185#define CMA_MB_FLHIGH_EXEC_SIZE 0x100000
186#define CMA_MB_FLHIGH_RDWR_BASE (CFG_CMA_MB_BASE+0xfc00000)
187#define CMA_MB_FLHIGH_RDWR_SIZE 0x400000
188#endif
189
190#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
191
192/* PCI Control Register bits */
193
194/* V360EPC Control register bits */
195#define CMA_MB_PCI_V3CTL_RESET 0x01
196#define CMA_MB_PCI_V3CTL_EXTADD 0x08
197
198/* PCI ID Select register bits */
199#define CMA_MB_PCI_IDSEL_SLOTA 0x01
200#define CMA_MB_PCI_IDSEL_SLOTB 0x02
201#define CMA_MB_PCI_IDSEL_GD82559 0x04
202#define CMA_MB_PCI_IDSEL_B69000 0x08
203#define CMA_MB_PCI_IDSEL_PD6832 0x10
204
205/* PCI Interrupt Mask/Status register bits */
206#define CMA_MB_PCI_IMS_INTA 0x01
207#define CMA_MB_PCI_IMS_INTB 0x02
208#define CMA_MB_PCI_IMS_INTC 0x04
209#define CMA_MB_PCI_IMS_INTD 0x08
210#define CMA_MB_PCI_IMS_CBINT 0x10
211#define CMA_MB_PCI_IMS_V3LINT 0x80
212
213#endif
214
215#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150)
216
217/*
218 * IREQ1 Interrupt Mask/Status register bits
219 * (Note: not available on CMA150 - must poll HT6542B interrupt register)
220 */
221
222#define IREQ1_MINT 0x01
223#define IREQ1_KINT 0x02
224#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
225#define IREQ1_SINT2 0x04
226#define IREQ1_SINT3 0x08
227#endif
228
229#endif
230
231#ifndef __ASSEMBLY__
232
233#include <asm/byteorder.h>
234
235/* a single CMA10x motherboard i/o register */
236typedef
237 struct {
238#if defined(__LITTLE_ENDIAN)
239 unsigned char value;
240#endif
241 unsigned char filler[7];
242#if defined(__BIG_ENDIAN)
243 unsigned char value;
244#endif
245 }
246cma_mb_reg;
247
248extern __inline__ unsigned char
249cma_mb_reg_read(volatile cma_mb_reg *reg)
250{
251 unsigned char data = reg->value;
252 __asm__ __volatile__ ("eieio" : : : "memory");
253 return data;
254}
255
256extern __inline__ void
257cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data)
258{
259 reg->value = data;
260 __asm__ __volatile__ ("eieio" : : : "memory");
261}
262
263#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
264
265/* MK48T02 RTC registers */
266typedef
267 struct {
268 cma_mb_reg sram[2040];/* Battery-Backed SRAM */
269 cma_mb_reg clk_ctl; /* Clock Control Register */
270 cma_mb_reg clk_sec; /* Clock Seconds Register */
271 cma_mb_reg clk_min; /* Clock Minutes Register */
272 cma_mb_reg clk_hour; /* Clock Hour Register */
273 cma_mb_reg clk_day; /* Clock Day Register */
274 cma_mb_reg clk_date; /* Clock Date Register */
275 cma_mb_reg clk_month; /* Clock Month Register */
276 cma_mb_reg clk_year; /* Clock Year Register */
277 }
278cma_mb_rtc;
279
280#endif
281
282#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
283
284/* ST16C522 Serial I/O */
285typedef
286 struct {
287 cma_mb_reg ser_rhr; /* Receive Holding Register (R, DLAB=0) */
288 cma_mb_reg ser_ier; /* Interrupt Enable Register (R/W, DLAB=0) */
289 cma_mb_reg ser_isr; /* Interrupt Status Register (R) */
290 cma_mb_reg ser_lcr; /* Line Control Register (R/W) */
291 cma_mb_reg ser_mcr; /* Modem Control Register (R/W) */
292 cma_mb_reg ser_lsr; /* Line Status Register (R) */
293 cma_mb_reg ser_msr; /* Modem Status Register (R/W) */
294 cma_mb_reg ser_spr; /* Scratch Pad Register (R/W) */
295 }
296cma_mb_serial;
297
298#define ser_thr ser_rhr /* Transmit Holding Register (W, DLAB=0) */
299#define ser_brl ser_rhr /* Baud Rate Divisor Low Byte (R/W, DLAB=1) */
300#define ser_brh ser_ier /* Baud Rate Divisor High Byte (R/W, DLAB=1) */
301#define ser_fcr ser_isr /* FIFO Control Register (W) */
302#define ser_nop ser_lsr /* No Operation (W) */
303
304/* ST16C522 Parallel I/O */
305typedef
306 struct {
307 cma_mb_reg par_rdr; /* Port Read Data Register (R) */
308 cma_mb_reg par_sr; /* Status Register (R) */
309 cma_mb_reg par_cmd; /* Command Register (R) */
310 }
311cma_mb_parallel;
312
313#define par_wdr par_rdr /* Port Write Data Register (W) */
314#define par_ios par_sr /* I/O Select Register (W) */
315#define par_ctl par_cmd /* Control Register (W) */
316
317#endif
318
319#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302)
320
321/* HT6542B PS/2 Keyboard/Mouse Controller */
322typedef
323 struct {
324 cma_mb_reg kbm_rdr; /* Read Data Register (R) */
325 cma_mb_reg kbm_sr; /* Status Register (R) */
326 }
327cma_mb_kbm;
328
329#define kbm_wdr kbm_rdr /* Write Data Register (W) */
330#define kbm_cmd kbm_sr /* Command Register (W) */
331
332#endif
333
334#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
335
336/* HD44780 LCD Display */
337typedef
338 struct {
339 cma_mb_reg lcd_ccr; /* Current Character Register (R/W) */
340 cma_mb_reg lcd_bsr; /* Busy Status Register (R) */
341 }
342cma_mb_lcd;
343
344#define lcd_cmd lcd_bsr /* Command Register (W) */
345
346#endif
347
348/* 8-Position Configuration Switch */
349typedef
350 struct {
351 cma_mb_reg dip_val; /* Dip Switch value (R) */
352 }
353cma_mb_dipsw;
354
355#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
356
357/* V360EPC PCI Bridge */
358typedef
359 struct {
360#if defined(__LITTLE_ENDIAN)
361 unsigned short v3_pci_vendor; /* 0x00 */
362 unsigned short v3_pci_device;
363 unsigned short v3_pci_cmd; /* 0x04 */
364 unsigned short v3_pci_stat;
365 unsigned long v3_pci_cc_rev; /* 0x08 */
366 unsigned long v3_pci_hdr_cfg; /* 0x0c */
367 unsigned long v3_pci_io_base; /* 0x10 */
368 unsigned long v3_pci_base0; /* 0x14 */
369 unsigned long v3_pci_base1; /* 0x18 */
370 unsigned long reserved1[4]; /* 0x1c */
371 unsigned short v3_pci_sub_vendor; /* 0x2c */
372 unsigned short v3_pci_sub_id;
373 unsigned long v3_pci_rom; /* 0x30 */
374 unsigned long reserved2[2]; /* 0x34 */
375 unsigned long v3_pci_bparam; /* 0x3c */
376 unsigned long v3_pci_map0; /* 0x40 */
377 unsigned long v3_pci_map1; /* 0x44 */
378 unsigned long v3_pci_int_stat; /* 0x48 */
379 unsigned long v3_pci_int_cfg; /* 0x4c */
380 unsigned long reserved3[1]; /* 0x50 */
381 unsigned long v3_lb_base0; /* 0x54 */
382 unsigned long v3_lb_base1; /* 0x58 */
383 unsigned short reserved4; /* 0x5c */
384 unsigned short v3_lb_map0;
385 unsigned short reserved5; /* 0x60 */
386 unsigned short v3_lb_map1;
387 unsigned short v3_lb_base2; /* 0x64 */
388 unsigned short v3_lb_map2;
389 unsigned long v3_lb_size; /* 0x68 */
390 unsigned short reserved6; /* 0x6c */
391 unsigned short v3_lb_io_base;
392 unsigned short v3_fifo_cfg; /* 0x70 */
393 unsigned short v3_fifo_priority;
394 unsigned short v3_fifo_stat; /* 0x74 */
395 unsigned char v3_lb_istat;
396 unsigned char v3_lb_imask;
397 unsigned short v3_system; /* 0x78 */
398 unsigned short v3_lb_cfg;
399 unsigned short v3_pci_cfg; /* 0x7c */
400 unsigned short reserved7;
401 unsigned long v3_dma_pci_addr0; /* 0x80 */
402 unsigned long v3_dma_local_addr0; /* 0x84 */
403 unsigned long v3_dma_length0:24; /* 0x88 */
404 unsigned long v3_dma_csr0:8;
405 unsigned long v3_dma_ctlb_adr0; /* 0x8c */
406 unsigned long v3_dma_pci_addr1; /* 0x90 */
407 unsigned long v3_dma_local_addr1; /* 0x94 */
408 unsigned long v3_dma_length1:24; /* 0x98 */
409 unsigned long v3_dma_csr1:8;
410 unsigned long v3_dma_ctlb_adr1; /* 0x9c */
411 unsigned long v3_i20_mups[8]; /* 0xa0 */
412 unsigned char v3_mail_data0; /* 0xc0 */
413 unsigned char v3_mail_data1;
414 unsigned char v3_mail_data2;
415 unsigned char v3_mail_data3;
416 unsigned char v3_mail_data4; /* 0xc4 */
417 unsigned char v3_mail_data5;
418 unsigned char v3_mail_data6;
419 unsigned char v3_mail_data7;
420 unsigned char v3_mail_data8; /* 0xc8 */
421 unsigned char v3_mail_data9;
422 unsigned char v3_mail_data10;
423 unsigned char v3_mail_data11;
424 unsigned char v3_mail_data12; /* 0xcc */
425 unsigned char v3_mail_data13;
426 unsigned char v3_mail_data14;
427 unsigned char v3_mail_data15;
428 unsigned short v3_pci_mail_iewr; /* 0xd0 */
429 unsigned short v3_pci_mail_ierd;
430 unsigned short v3_lb_mail_iewr; /* 0xd4 */
431 unsigned short v3_lb_mail_ierd;
432 unsigned short v3_mail_wr_stat; /* 0xd8 */
433 unsigned short v3_mail_rd_stat;
434 unsigned long v3_qba_map; /* 0xdc */
435 unsigned long v3_dma_delay:8; /* 0xe0 */
436 unsigned long reserved8:24;
437 unsigned long reserved9[7]; /* 0xe4 */
438#endif
439#if defined(__BIG_ENDIAN)
440 unsigned short v3_pci_device; /* 0x00 */
441 unsigned short v3_pci_vendor;
442 unsigned short v3_pci_stat; /* 0x04 */
443 unsigned short v3_pci_cmd;
444 unsigned long v3_pci_cc_rev; /* 0x08 */
445 unsigned long v3_pci_hdr_cfg; /* 0x0c */
446 unsigned long v3_pci_io_base; /* 0x10 */
447 unsigned long v3_pci_base0; /* 0x14 */
448 unsigned long v3_pci_base1; /* 0x18 */
449 unsigned long reserved1[4]; /* 0x1c */
450 unsigned short v3_pci_sub_id; /* 0x2c */
451 unsigned short v3_pci_sub_vendor;
452 unsigned long v3_pci_rom; /* 0x30 */
453 unsigned long reserved2[2]; /* 0x34 */
454 unsigned long v3_pci_bparam; /* 0x3c */
455 unsigned long v3_pci_map0; /* 0x40 */
456 unsigned long v3_pci_map1; /* 0x44 */
457 unsigned long v3_pci_int_stat; /* 0x48 */
458 unsigned long v3_pci_int_cfg; /* 0x4c */
459 unsigned long reserved3; /* 0x50 */
460 unsigned long v3_lb_base0; /* 0x54 */
461 unsigned long v3_lb_base1; /* 0x58 */
462 unsigned short v3_lb_map0; /* 0x5c */
463 unsigned short reserved4;
464 unsigned short v3_lb_map1; /* 0x60 */
465 unsigned short reserved5;
466 unsigned short v3_lb_map2; /* 0x64 */
467 unsigned short v3_lb_base2;
468 unsigned long v3_lb_size; /* 0x68 */
469 unsigned short v3_lb_io_base; /* 0x6c */
470 unsigned short reserved6;
471 unsigned short v3_fifo_priority; /* 0x70 */
472 unsigned short v3_fifo_cfg;
473 unsigned char v3_lb_imask; /* 0x74 */
474 unsigned char v3_lb_istat;
475 unsigned short v3_fifo_stat;
476 unsigned short v3_lb_cfg; /* 0x78 */
477 unsigned short v3_system;
478 unsigned short reserved7; /* 0x7c */
479 unsigned short v3_pci_cfg;
480 unsigned long v3_dma_pci_addr0; /* 0x80 */
481 unsigned long v3_dma_local_addr0; /* 0x84 */
482 unsigned long v3_dma_csr0:8; /* 0x88 */
483 unsigned long v3_dma_length0:24;
484 unsigned long v3_dma_ctlb_adr0; /* 0x8c */
485 unsigned long v3_dma_pci_addr1; /* 0x90 */
486 unsigned long v3_dma_local_addr1; /* 0x94 */
487 unsigned long v3_dma_csr1:8; /* 0x98 */
488 unsigned long v3_dma_length1:24;
489 unsigned long v3_dma_ctlb_adr1; /* 0x9c */
490 unsigned long v3_i20_mups[8]; /* 0xa0 */
491 unsigned char v3_mail_data3; /* 0xc0 */
492 unsigned char v3_mail_data2;
493 unsigned char v3_mail_data1;
494 unsigned char v3_mail_data0;
495 unsigned char v3_mail_data7; /* 0xc4 */
496 unsigned char v3_mail_data6;
497 unsigned char v3_mail_data5;
498 unsigned char v3_mail_data4;
499 unsigned char v3_mail_data11; /* 0xc8 */
500 unsigned char v3_mail_data10;
501 unsigned char v3_mail_data9;
502 unsigned char v3_mail_data8;
503 unsigned char v3_mail_data15; /* 0xcc */
504 unsigned char v3_mail_data14;
505 unsigned char v3_mail_data13;
506 unsigned char v3_mail_data12;
507 unsigned short v3_pci_mail_ierd; /* 0xd0 */
508 unsigned short v3_pci_mail_iewr;
509 unsigned short v3_lb_mail_ierd; /* 0xd4 */
510 unsigned short v3_lb_mail_iewr;
511 unsigned short v3_mail_rd_stat; /* 0xd8 */
512 unsigned short v3_mail_wr_stat;
513 unsigned long v3_qba_map; /* 0xdc */
514 unsigned long reserved8:24; /* 0xe0 */
515 unsigned long v3_dma_delay:8;
516 unsigned long reserved9[7]; /* 0xe4 */
517#endif
518 } /* 0x100 */
519cma_mb_v360epc;
520
521#endif
522
523#endif /* __ASSEMBLY__ */
524
525#endif /* _COGENT_MB_H */