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Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2020 Hitachi Power Grids. All rights reserved.
4 */
5
6#ifndef __CONFIG_PG_WCOM_LS102XA_H
7#define __CONFIG_PG_WCOM_LS102XA_H
8
Tom Rini6a5dccc2022-11-16 13:10:41 -05009#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
10#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000011
Tom Rini0bb9b092022-12-04 10:13:37 -050012#define CFG_PRAM ((CONFIG_KM_PNVRAM + \
Aleksandar Gerasimovski68a89982021-06-08 14:19:08 +000013 CONFIG_KM_PHRAM + \
14 CONFIG_KM_RESERVED_PRAM) >> 10)
15
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000016#define PHYS_SDRAM 0x80000000
17#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
18
Tom Rini6a5dccc2022-11-16 13:10:41 -050019#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
20#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000021
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000022#define SPD_EEPROM_ADDRESS 0x54
23
Aleksandar Gerasimovskibece73e2021-06-08 14:17:34 +000024/* POST memory regions test */
Tom Rini8eaa3c72022-11-19 18:45:44 -050025#define CFG_POST (CFG_SYS_POST_MEM_REGIONS)
26#define CFG_POST_EXTERNAL_WORD_FUNCS
Aleksandar Gerasimovskibece73e2021-06-08 14:17:34 +000027
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000028/*
29 * IFC Definitions
30 */
31/* NOR Flash Definitions */
Tom Rini6a5dccc2022-11-16 13:10:41 -050032#define CFG_SYS_FLASH_BASE 0x60000000
33#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000034
Tom Rini6a5dccc2022-11-16 13:10:41 -050035#define CFG_SYS_NOR0_CSPR_EXT (0x0)
36#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000037 CSPR_PORT_SIZE_16 | \
38 CSPR_TE | \
39 CSPR_MSEL_NOR | \
40 CSPR_V)
Tom Rini7b577ba2022-11-16 13:10:25 -050041#define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000042
Tom Rini7b577ba2022-11-16 13:10:25 -050043#define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000044 CSOR_NOR_ADM_SHIFT(0x4) | \
45 CSOR_NOR_NOR_MODE_ASYNC_NOR | \
46 CSOR_NOR_TRHZ_20 | \
47 CSOR_NOR_BCTLD)
Tom Rini7b577ba2022-11-16 13:10:25 -050048#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000049 FTIM0_NOR_TEADC(0x7) | \
50 FTIM0_NOR_TAVDS(0x0) | \
51 FTIM0_NOR_TEAHC(0x1))
Tom Rini7b577ba2022-11-16 13:10:25 -050052#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000053 FTIM1_NOR_TRAD_NOR(0x21) | \
54 FTIM1_NOR_TSEQRAD_NOR(0x21))
Tom Rini7b577ba2022-11-16 13:10:25 -050055#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000056 FTIM2_NOR_TCH(0x1) | \
57 FTIM2_NOR_TWPH(0x6) | \
58 FTIM2_NOR_TWP(0xb))
Tom Rini7b577ba2022-11-16 13:10:25 -050059#define CFG_SYS_NOR_FTIM3 0
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000060
Tom Rini6a5dccc2022-11-16 13:10:41 -050061#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000062
Tom Rini6a5dccc2022-11-16 13:10:41 -050063#define CFG_SYS_WRITE_SWAPPED_DATA
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000064
Tom Rini6a5dccc2022-11-16 13:10:41 -050065#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
66#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
67#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
68#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
69#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
70#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
71#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
72#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000073
74/* NAND Flash Definitions */
Tom Rinib4213492022-11-12 17:36:51 -050075#define CFG_SYS_NAND_BASE 0x68000000
76#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000077
Tom Rinib4213492022-11-12 17:36:51 -050078#define CFG_SYS_NAND_CSPR_EXT (0x0)
79#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000080 CSPR_PORT_SIZE_8 | \
81 CSPR_TE | \
82 CSPR_MSEL_NAND | \
83 CSPR_V)
Tom Rinib4213492022-11-12 17:36:51 -050084#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
85#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000086 | CSOR_NAND_ECC_DEC_EN \
87 | CSOR_NAND_ECC_MODE_4 \
88 | CSOR_NAND_RAL_3 \
89 | CSOR_NAND_PGS_2K \
90 | CSOR_NAND_SPRZ_64 \
91 | CSOR_NAND_PB(64) \
92 | CSOR_NAND_TRHZ_40 \
93 | CSOR_NAND_BCTLD)
94
Tom Rinib4213492022-11-12 17:36:51 -050095#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +000096 FTIM0_NAND_TWP(0x8) | \
97 FTIM0_NAND_TWCHT(0x3) | \
98 FTIM0_NAND_TWH(0x5))
Tom Rinib4213492022-11-12 17:36:51 -050099#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000100 FTIM1_NAND_TWBE(0x1e) | \
101 FTIM1_NAND_TRR(0x6) | \
102 FTIM1_NAND_TRP(0x8))
Tom Rinib4213492022-11-12 17:36:51 -0500103#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000104 FTIM2_NAND_TREH(0x5) | \
105 FTIM2_NAND_TWHRE(0x3c))
Tom Rinib4213492022-11-12 17:36:51 -0500106#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000107
Tom Rini6a5dccc2022-11-16 13:10:41 -0500108#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
109#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
110#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
111#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
112#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
113#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
114#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
115#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000116
Tom Rinib4213492022-11-12 17:36:51 -0500117#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000118
119/* QRIO FPGA Definitions */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500120#define CFG_SYS_QRIO_BASE 0x70000000
121#define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000122
Tom Rini6a5dccc2022-11-16 13:10:41 -0500123#define CFG_SYS_CSPR2_EXT (0x00)
124#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000125 CSPR_PORT_SIZE_8 | \
126 CSPR_TE | \
127 CSPR_MSEL_GPCM | \
128 CSPR_V)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500129#define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024)
130#define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000131 CSOR_GPCM_TRHZ_20 | \
132 CSOR_GPCM_BCTLD)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500133#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000134 FTIM0_GPCM_TEADC(0x8) | \
135 FTIM0_GPCM_TEAHC(0x2))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500136#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000137 FTIM1_GPCM_TRAD(0x6))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500138#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000139 FTIM2_GPCM_TCH(0x1) | \
140 FTIM2_GPCM_TWP(0x7))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500141#define CFG_SYS_CS2_FTIM3 0x04000000
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000142
143/*
144 * Serial Port
145 */
Tom Rinidf6a2152022-11-16 13:10:28 -0500146#define CFG_SYS_NS16550_CLK get_serial_clock()
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000147
Tom Rinib942f0a2022-12-04 10:13:54 -0500148#define CFG_SMP_PEN_ADDR 0x01ee0200
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000149
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000150#define HWCONFIG_BUFFER_SIZE 256
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000151
Tom Rini6a5dccc2022-11-16 13:10:41 -0500152#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000153
Aleksandar Gerasimovski032bdbc2021-02-22 18:18:11 +0000154#endif