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git01.mediatek.com / filogic / uboot / 1d52512b2e81dbfae2cf11f6ef886bc22a7cd4d8 / . / dts / upstream / Bindings / pinctrl / nvidia,tegra20-pinmux.yaml
blob: 63cd743a30e002ab2f7cf4ce7030b0a71609a739 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra20 Pinmux Controller
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14 compatible:
15 const: nvidia,tegra20-pinmux
16
17 reg:
18 items:
19 - description: tri-state registers
20 - description: mux register
21 - description: pull-up/down registers
22 - description: pad control registers
23
24patternProperties:
25 "^pinmux(-[a-z0-9-_]+)?$":
26 type: object
27
28 # pin groups
29 additionalProperties:
30 $ref: nvidia,tegra-pinmux-common.yaml
31 additionalProperties: false
32 properties:
33 nvidia,pins:
34 items:
35 enum: [ ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1,
36 dap2, dap3, dap4, ddc, dta, dtb, dtc, dtd, dte, dtf, gma,
37 gmb, gmc, gmd, gme, gpu, gpu7, gpv, hdint, i2cp, irrx,
38 irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, ld0, ld1,
39 ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12,
40 ld13, ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2,
41 lhs, lm0, lm1, lpp, lpw0, lpw1, lpw2, lsc0, lsc1, lsck,
42 lsda, lsdi, lspi, lvp0, lvp1, lvs, owc, pmc, pta, rm, sdb,
43 sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, spdo, spia,
44 spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac,
45 uad, uca, ucb, uda,
46 # tristate groups
47 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls,
48 lc, ld17_0, ld19_18, ld21_20, ld23_22,
49 # drive groups
50 drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1,
51 drive_cdev2, drive_csus, drive_dap1, drive_dap2,
52 drive_dap3, drive_dap4, drive_dbg, drive_lcd1, drive_lcd2,
53 drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
54 drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2,
55 drive_xm2a, drive_xm2c, drive_xm2d, drive_xm2clk,
56 drive_sdio1, drive_crt, drive_ddc, drive_gma, drive_gmb,
57 drive_gmc, drive_gmd, drive_gme, drive_owr, drive_uda ]
58
59 nvidia,function:
60 enum: [ ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4,
61 dap5, displaya, displayb, emc_test0_dll, emc_test1_dll, gmi,
62 gmi_int, hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio,
63 mipi_hs, nand, osc, owr, pcie, plla_out, pllc_out1,
64 pllm_out1, pllp_out2, pllp_out3, pllp_out4, pwm, pwr_intr,
65 pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck, sdio1, sdio2,
66 sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt, spi3,
67 spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
68 vi, vi_sensor_clk, xio ]
69
70 nvidia,pull: true
71 nvidia,tristate: true
72 nvidia,schmitt: true
73 nvidia,pull-down-strength: true
74 nvidia,pull-up-strength: true
75 nvidia,high-speed-mode: true
76 nvidia,low-power-mode: true
77 nvidia,slew-rate-rising: true
78 nvidia,slew-rate-falling: true
79
80 required:
81 - nvidia,pins
82
83additionalProperties: false
84
85required:
86 - compatible
87 - reg
88
89examples:
90 - |
91 #include <dt-bindings/clock/tegra20-car.h>
92 #include <dt-bindings/interrupt-controller/arm-gic.h>
93
94 pinctrl@70000000 {
95 compatible = "nvidia,tegra20-pinmux";
96 reg = <0x70000014 0x10>, /* Tri-state registers */
97 <0x70000080 0x20>, /* Mux registers */
98 <0x700000a0 0x14>, /* Pull-up/down registers */
99 <0x70000868 0xa8>; /* Pad control registers */
100
101 pinmux {
102 atb {
103 nvidia,pins = "atb", "gma", "gme";
104 nvidia,function = "sdio4";
105 nvidia,pull = <0>;
106 nvidia,tristate = <0>;
107 };
108 };
109 };
110...