dts/upstream/Bindings/pci/brcm,iproc-pcie.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom iProc PCIe controller with the platform bus interface

maintainers:
  - Ray Jui <ray.jui@broadcom.com>
  - Scott Branden <scott.branden@broadcom.com>

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#

properties:
  compatible:
    items:
      - enum:
          # for the first generation of PAXB based controller, used in SoCs
          # including NSP, Cygnus, NS2, and Pegasus
          - brcm,iproc-pcie
          # for the second generation of PAXB-based controllers, used in
          # Stingray
          - brcm,iproc-pcie-paxb-v2
          # For the first generation of PAXC based controller, used in NS2
          - brcm,iproc-pcie-paxc
          # For the second generation of PAXC based controller, used in Stingray
          - brcm,iproc-pcie-paxc-v2

  reg:
    maxItems: 1
    description: >
       Base address and length of the PCIe controller I/O register space

  ranges:
    minItems: 1
    maxItems: 2
    description: >
      Ranges for the PCI memory and I/O regions

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: pcie-phy

  dma-coherent: true

  brcm,pcie-ob:
    type: boolean
    description: >
      Some iProc SoCs do not have the outbound address mapping done by the
      ASIC after power on reset. In this case, SW needs to configure it

  brcm,pcie-ob-axi-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: >
       The offset from the AXI address to the internal address used by the
       iProc PCIe core (not the PCIe address)

  msi:
    type: object
    $ref: /schemas/interrupt-controller/msi-controller.yaml#
    unevaluatedProperties: false

    properties:
      compatible:
        items:
          - const: brcm,iproc-msi

      interrupts:
        maxItems: 4

      brcm,pcie-msi-inten:
        type: boolean
        description:
          Needs to be present for some older iProc platforms that require the
          interrupt enable registers to be set explicitly to enable MSI

  msi-parent: true

dependencies:
  brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"]
  brcm,pcie-msi-inten: [msi-controller]

required:
  - compatible
  - reg
  - ranges

if:
  properties:
    compatible:
      contains:
        enum:
          - brcm,iproc-pcie
then:
  required:
    - interrupt-map
    - interrupt-map-mask

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gic: interrupt-controller {
        interrupt-controller;
        #interrupt-cells = <3>;
    };

    pcie@18012000 {
        compatible = "brcm,iproc-pcie";
        reg = <0x18012000 0x1000>;

        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 0>;
        interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;

        linux,pci-domain = <0>;

        bus-range = <0x00 0xff>;

        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        ranges = <0x81000000 0          0 0x28000000 0 0x00010000>,
                 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;

        phys = <&phy 0 5>;
        phy-names = "pcie-phy";

        brcm,pcie-ob;
        brcm,pcie-ob-axi-offset = <0x00000000>;

        msi-parent = <&msi0>;

        /* iProc event queue based MSI */
        msi0: msi {
            compatible = "brcm,iproc-msi";
            msi-controller;
            interrupt-parent = <&gic>;
            interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
                    <GIC_SPI 97 IRQ_TYPE_NONE>,
                    <GIC_SPI 98 IRQ_TYPE_NONE>,
                    <GIC_SPI 99 IRQ_TYPE_NONE>;
        };
    };
  - |
    pcie@18013000 {
        compatible = "brcm,iproc-pcie";
        reg = <0x18013000 0x1000>;

        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 0>;
        interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;

        linux,pci-domain = <1>;

        bus-range = <0x00 0xff>;

        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        ranges = <0x81000000 0          0 0x48000000 0 0x00010000>,
                 <0x82000000 0 0x40000000 0x40000000 0 0x04000000>;

        phys = <&phy 1 6>;
        phy-names = "pcie-phy";
    };