blob: 0b25e5893b3cbaf9711eb36796c826a30b562bee [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +05302/*
3 * Microchip PIC32 MUSB "glue layer"
4 *
5 * Copyright (C) 2015, Microchip Technology Inc.
6 * Cristian Birsan <cristian.birsan@microchip.com>
7 * Purna Chandra Mandal <purna.mandal@microchip.com>
8 *
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +05309 * Based on the dsps "glue layer" code.
10 */
11
Simon Glass61adc042020-07-19 10:15:55 -060012#include <dm.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060015#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060016#include <linux/delay.h>
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +053017#include <linux/usb/musb.h>
18#include "linux-compat.h"
19#include "musb_core.h"
20#include "musb_uboot.h"
21
22DECLARE_GLOBAL_DATA_PTR;
23
24#define PIC32_TX_EP_MASK 0x0f /* EP0 + 7 Tx EPs */
25#define PIC32_RX_EP_MASK 0x0e /* 7 Rx EPs */
26
27#define MUSB_SOFTRST 0x7f
28#define MUSB_SOFTRST_NRST BIT(0)
29#define MUSB_SOFTRST_NRSTX BIT(1)
30
31#define USBCRCON 0
32#define USBCRCON_USBWKUPEN BIT(0) /* Enable Wakeup Interrupt */
33#define USBCRCON_USBRIE BIT(1) /* Enable Remote resume Interrupt */
34#define USBCRCON_USBIE BIT(2) /* Enable USB General interrupt */
35#define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring */
36#define USBCRCON_BSVALMONEN BIT(4) /* Enable B-Device VBUS monitoring */
37#define USBCRCON_ASVALMONEN BIT(5) /* Enable A-Device VBUS monitoring */
38#define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
39#define USBCRCON_PHYIDEN BIT(7) /* PHY ID monitoring enable */
40#define USBCRCON_USBIDVAL BIT(8) /* USB ID value */
41#define USBCRCON_USBIDOVEN BIT(9) /* USB ID override enable */
42#define USBCRCON_USBWK BIT(24) /* USB Wakeup Status */
43#define USBCRCON_USBRF BIT(25) /* USB Resume Status */
44#define USBCRCON_USBIF BIT(26) /* USB General Interrupt Status */
45
46/* PIC32 controller data */
47struct pic32_musb_data {
48 struct musb_host_data mdata;
49 struct device dev;
50 void __iomem *musb_glue;
51};
52
53#define to_pic32_musb_data(d) \
54 container_of(d, struct pic32_musb_data, dev)
55
56static void pic32_musb_disable(struct musb *musb)
57{
58 /* no way to shut the controller */
59}
60
61static int pic32_musb_enable(struct musb *musb)
62{
63 /* soft reset by NRSTx */
64 musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
65 /* set mode */
66 musb_platform_set_mode(musb, musb->board_mode);
67
68 return 0;
69}
70
71static irqreturn_t pic32_interrupt(int irq, void *hci)
72{
73 struct musb *musb = hci;
74 irqreturn_t ret = IRQ_NONE;
75 u32 epintr, usbintr;
76
77 /* ack usb core interrupts */
78 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
79 if (musb->int_usb)
80 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
81
82 /* ack endpoint interrupts */
83 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
84 if (musb->int_rx)
85 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
86
87 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
88 if (musb->int_tx)
89 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
90
91 /* drop spurious RX and TX if device is disconnected */
92 if (musb->int_usb & MUSB_INTR_DISCONNECT) {
93 musb->int_tx = 0;
94 musb->int_rx = 0;
95 }
96
97 if (musb->int_tx || musb->int_rx || musb->int_usb)
98 ret = musb_interrupt(musb);
99
100 return ret;
101}
102
103static int pic32_musb_set_mode(struct musb *musb, u8 mode)
104{
105 struct device *dev = musb->controller;
106 struct pic32_musb_data *pdata = to_pic32_musb_data(dev);
107
108 switch (mode) {
109 case MUSB_HOST:
110 clrsetbits_le32(pdata->musb_glue + USBCRCON,
111 USBCRCON_USBIDVAL, USBCRCON_USBIDOVEN);
112 break;
113 case MUSB_PERIPHERAL:
114 setbits_le32(pdata->musb_glue + USBCRCON,
115 USBCRCON_USBIDVAL | USBCRCON_USBIDOVEN);
116 break;
117 case MUSB_OTG:
118 dev_err(dev, "support for OTG is unimplemented\n");
119 break;
120 default:
121 dev_err(dev, "unsupported mode %d\n", mode);
122 return -EINVAL;
123 }
124
125 return 0;
126}
127
128static int pic32_musb_init(struct musb *musb)
129{
130 struct pic32_musb_data *pdata = to_pic32_musb_data(musb->controller);
131 u32 ctrl, hwvers;
132 u8 power;
133
134 /* Returns zero if not clocked */
135 hwvers = musb_read_hwvers(musb->mregs);
136 if (!hwvers)
137 return -ENODEV;
138
139 /* Reset the musb */
140 power = musb_readb(musb->mregs, MUSB_POWER);
141 power = power | MUSB_POWER_RESET;
142 musb_writeb(musb->mregs, MUSB_POWER, power);
143 mdelay(100);
144
145 /* Start the on-chip PHY and its PLL. */
146 power = power & ~MUSB_POWER_RESET;
147 musb_writeb(musb->mregs, MUSB_POWER, power);
148
149 musb->isr = pic32_interrupt;
150
151 ctrl = USBCRCON_USBIF | USBCRCON_USBRF |
152 USBCRCON_USBWK | USBCRCON_USBIDOVEN |
153 USBCRCON_PHYIDEN | USBCRCON_USBIE |
154 USBCRCON_USBRIE | USBCRCON_USBWKUPEN |
155 USBCRCON_VBUSMONEN;
156 writel(ctrl, pdata->musb_glue + USBCRCON);
157
158 return 0;
159}
160
161/* PIC32 supports only 32bit read operation */
162void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
163{
164 void __iomem *fifo = hw_ep->fifo;
165 u32 val, rem = len % 4;
166
167 /* USB stack ensures dst is always 32bit aligned. */
168 readsl(fifo, dst, len / 4);
169 if (rem) {
170 dst += len & ~0x03;
171 val = musb_readl(fifo, 0);
172 memcpy(dst, &val, rem);
173 }
174}
175
176const struct musb_platform_ops pic32_musb_ops = {
177 .init = pic32_musb_init,
178 .set_mode = pic32_musb_set_mode,
179 .disable = pic32_musb_disable,
180 .enable = pic32_musb_enable,
181};
182
183/* PIC32 default FIFO config - fits in 8KB */
184static struct musb_fifo_cfg pic32_musb_fifo_config[] = {
185 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
186 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
187 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
188 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
189 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
190 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
191 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
192 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
193 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
194 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
195 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
196 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
197 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
198 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
199};
200
201static struct musb_hdrc_config pic32_musb_config = {
202 .fifo_cfg = pic32_musb_fifo_config,
203 .fifo_cfg_size = ARRAY_SIZE(pic32_musb_fifo_config),
204 .multipoint = 1,
205 .dyn_fifo = 1,
206 .num_eps = 8,
207 .ram_bits = 11,
208};
209
210/* PIC32 has one MUSB controller which can be host or gadget */
211static struct musb_hdrc_platform_data pic32_musb_plat = {
212 .mode = MUSB_HOST,
213 .config = &pic32_musb_config,
214 .power = 250, /* 500mA */
215 .platform_ops = &pic32_musb_ops,
216};
217
218static int musb_usb_probe(struct udevice *dev)
219{
220 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
221 struct pic32_musb_data *pdata = dev_get_priv(dev);
222 struct musb_host_data *mdata = &pdata->mdata;
223 struct fdt_resource mc, glue;
224 void *fdt = (void *)gd->fdt_blob;
Simon Glassdd79d6e2017-01-17 16:52:55 -0700225 int node = dev_of_offset(dev);
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +0530226 void __iomem *mregs;
227 int ret;
228
229 priv->desc_before_addr = true;
230
231 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
232 "mc", &mc);
233 if (ret < 0) {
234 printf("pic32-musb: resource \"mc\" not found\n");
235 return ret;
236 }
237
238 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
239 "control", &glue);
240 if (ret < 0) {
241 printf("pic32-musb: resource \"control\" not found\n");
242 return ret;
243 }
244
245 mregs = ioremap(mc.start, fdt_resource_size(&mc));
246 pdata->musb_glue = ioremap(glue.start, fdt_resource_size(&glue));
247
248 /* init controller */
249#ifdef CONFIG_USB_MUSB_HOST
250 mdata->host = musb_init_controller(&pic32_musb_plat,
251 &pdata->dev, mregs);
252 if (!mdata->host)
253 return -EIO;
254
255 ret = musb_lowlevel_init(mdata);
256#else
257 pic32_musb_plat.mode = MUSB_PERIPHERAL;
Jagan Tekif0a6d792018-07-20 12:43:56 +0530258 mdata->host = musb_register(&pic32_musb_plat, &pdata->dev, mregs);
259 if (!mdata->host)
260 return -EIO;
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +0530261#endif
Jagan Tekif0a6d792018-07-20 12:43:56 +0530262 if ((ret == 0) && mdata->host)
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +0530263 printf("PIC32 MUSB OTG\n");
264
265 return ret;
266}
267
268static int musb_usb_remove(struct udevice *dev)
269{
270 struct pic32_musb_data *pdata = dev_get_priv(dev);
271
272 musb_stop(pdata->mdata.host);
273
274 return 0;
275}
276
277static const struct udevice_id pic32_musb_ids[] = {
278 { .compatible = "microchip,pic32mzda-usb" },
279 { }
280};
281
282U_BOOT_DRIVER(usb_musb) = {
283 .name = "pic32-musb",
284 .id = UCLASS_USB,
285 .of_match = pic32_musb_ids,
286 .probe = musb_usb_probe,
287 .remove = musb_usb_remove,
288#ifdef CONFIG_USB_MUSB_HOST
289 .ops = &musb_usb_ops,
290#endif
Simon Glassb75b15b2020-12-03 16:55:23 -0700291 .plat_auto = sizeof(struct usb_plat),
Simon Glass8a2b47f2020-12-03 16:55:17 -0700292 .priv_auto = sizeof(struct pic32_musb_data),
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +0530293};