blob: 3484ae1d21ee78ede669a945616081f643f139c1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ramneek Mehreshf4de4072015-05-29 14:47:19 +05302/*
Rajesh Bhagat885f29a2016-07-01 18:51:47 +05303 * Copyright 2015,2016 Freescale Semiconductor, Inc.
Ramneek Mehreshf4de4072015-05-29 14:47:19 +05304 *
5 * FSL USB HOST xHCI Controller
6 *
7 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
Ramneek Mehreshf4de4072015-05-29 14:47:19 +05308 */
9
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053011#include <usb.h>
Masahiro Yamada64e4f7f2016-09-21 11:28:57 +090012#include <linux/errno.h>
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053013#include <linux/compat.h>
14#include <linux/usb/xhci-fsl.h>
15#include <linux/usb/dwc3.h>
Jean-Jacques Hiblotad4142b2019-09-11 11:33:46 +020016#include <usb/xhci.h>
Sriram Dash01820952016-06-13 09:58:36 +053017#include <fsl_errata.h>
18#include <fsl_usb.h>
Rajesh Bhagat885f29a2016-07-01 18:51:47 +053019#include <dm.h>
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053020
21/* Declare global data pointer */
Rajesh Bhagat885f29a2016-07-01 18:51:47 +053022struct xhci_fsl_priv {
23 struct xhci_ctrl xhci;
24 fdt_addr_t hcd_base;
25 struct fsl_xhci ctx;
26};
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053027
28__weak int __board_usb_init(int index, enum usb_init_type init)
29{
30 return 0;
31}
32
Sriram Dash01820952016-06-13 09:58:36 +053033static int erratum_a008751(void)
34{
Priyanka Jain75cd67f2017-04-27 15:08:07 +053035#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
36 defined(CONFIG_TARGET_LS2080AQDS)
Sriram Dash01820952016-06-13 09:58:36 +053037 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
38 writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
39 return 0;
40#endif
41 return 1;
42}
43
44static void fsl_apply_xhci_errata(void)
45{
46 int ret;
47 if (has_erratum_a008751()) {
48 ret = erratum_a008751();
49 if (ret != 0)
50 puts("Failed to apply erratum a008751\n");
51 }
52}
53
Sriram Dash16f1d2b2016-08-22 17:55:15 +053054static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
55{
56 clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,
57 USB3_ENABLE_BEAT_BURST);
58 setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);
59}
60
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053061static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
62{
63 int ret = 0;
64
65 ret = dwc3_core_init(fsl_xhci->dwc3_reg);
66 if (ret) {
67 debug("%s:failed to initialize core\n", __func__);
68 return ret;
69 }
70
71 /* We are hard-coding DWC3 core to Host Mode */
72 dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
73
Nikhil Badola807babb2015-06-23 09:17:49 +053074 /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
75 dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
76
Sriram Dash16f1d2b2016-08-22 17:55:15 +053077 /* Change beat burst and outstanding pipelined transfers requests */
78 fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
79
Sriram Dasha1f422e2016-09-23 12:57:52 +053080 /*
81 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
82 * reliably support Rx Detect in P3 mode(P3 is the default
83 * setting). Therefore, some USB3.0 devices may not be detected
84 * reliably in Super Speed mode. So, USB controller to configure
85 * USB in P2 mode whenever the Receive Detect feature is required.
86 * whenever the Receive Detect feature is required.
87 */
88 if (has_erratum_a010151())
89 clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
90 DWC3_GUSB3PIPECTL_DISRXDETP3,
91 DWC3_GUSB3PIPECTL_DISRXDETP3);
92
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053093 return ret;
94}
95
96static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
97{
98 /*
99 * Currently fsl socs do not support PHY shutdown from
100 * sw. But this support may be added in future socs.
101 */
102 return 0;
103}
104
Rajesh Bhagat885f29a2016-07-01 18:51:47 +0530105static int xhci_fsl_probe(struct udevice *dev)
106{
107 struct xhci_fsl_priv *priv = dev_get_priv(dev);
108 struct xhci_hccr *hccr;
109 struct xhci_hcor *hcor;
110
111 int ret = 0;
112
113 /*
114 * Get the base address for XHCI controller from the device node
115 */
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900116 priv->hcd_base = dev_read_addr(dev);
Rajesh Bhagat885f29a2016-07-01 18:51:47 +0530117 if (priv->hcd_base == FDT_ADDR_T_NONE) {
118 debug("Can't get the XHCI register base address\n");
119 return -ENXIO;
120 }
121 priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base;
122 priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) +
123 DWC3_REG_OFFSET);
124
125 fsl_apply_xhci_errata();
126
127 ret = fsl_xhci_core_init(&priv->ctx);
128 if (ret < 0) {
129 puts("Failed to initialize xhci\n");
130 return ret;
131 }
132
133 hccr = (struct xhci_hccr *)(priv->ctx.hcd);
134 hcor = (struct xhci_hcor *)((uintptr_t) hccr
135 + HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
136
137 debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n",
138 (uintptr_t)hccr, (uintptr_t)hcor,
139 (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
140
141 return xhci_register(dev, hccr, hcor);
142}
143
144static int xhci_fsl_remove(struct udevice *dev)
145{
146 struct xhci_fsl_priv *priv = dev_get_priv(dev);
Rajesh Bhagat885f29a2016-07-01 18:51:47 +0530147
148 fsl_xhci_core_exit(&priv->ctx);
149
Masahiro Yamada9b70df52016-09-06 22:17:35 +0900150 return xhci_deregister(dev);
Rajesh Bhagat885f29a2016-07-01 18:51:47 +0530151}
152
153static const struct udevice_id xhci_usb_ids[] = {
154 { .compatible = "fsl,layerscape-dwc3", },
Michael Walle3ae724c2021-10-13 18:14:21 +0200155 { .compatible = "fsl,ls1028a-dwc3", },
Rajesh Bhagat885f29a2016-07-01 18:51:47 +0530156 { }
157};
158
159U_BOOT_DRIVER(xhci_fsl) = {
160 .name = "xhci_fsl",
161 .id = UCLASS_USB,
162 .of_match = xhci_usb_ids,
163 .probe = xhci_fsl_probe,
164 .remove = xhci_fsl_remove,
165 .ops = &xhci_usb_ops,
Simon Glassb75b15b2020-12-03 16:55:23 -0700166 .plat_auto = sizeof(struct usb_plat),
Simon Glass8a2b47f2020-12-03 16:55:17 -0700167 .priv_auto = sizeof(struct xhci_fsl_priv),
Rajesh Bhagat885f29a2016-07-01 18:51:47 +0530168 .flags = DM_FLAG_ALLOC_PRIV_DMA,
169};