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git01.mediatek.com / filogic / uboot / 1d52512b2e81dbfae2cf11f6ef886bc22a7cd4d8 / . / drivers / ram / starfive / ddrcsr_boot.c
blob: 6764b3ed5cc918a56979c85d34c85f1a998ebd61 [file] [log] [blame]
Yanhong Wangd60e8802023-03-29 11:42:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
5 */
6
Yanhong Wangd60e8802023-03-29 11:42:16 +0800[diff] [blame]7#include <asm/io.h>
8#include <asm/arch/regs.h>
9#include <linux/delay.h>
10#include <wait_bit.h>
11
12#include "starfive_ddr.h"
13
14#define REGOFFSET(offset) ((offset) / 4)
15
16static const struct ddr_reg_cfg ddr_csr_cfg[] = {
17 {0x0, 0x0, 0x00000001, REGSETALL},
18 {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG4G | REG8G)},
19 {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG2G)},
20 {0xf04, 0x0, 0x00000001, (OFFSET_SEL | F_SET | REG4G | REG8G)},
21 {0xf04, 0x0, 0x00800001, (OFFSET_SEL | F_SET | REG2G)},
22 {0xf10, 0x0, 0x00400000, (OFFSET_SEL | REGSETALL)},
23 {0xf14, 0x0, 0x043fffff, (OFFSET_SEL | REGSETALL)},
24 {0xf18, 0x0, 0x00000000, (OFFSET_SEL | REGSETALL)},
25 {0xf30, 0x0, 0x1f000041, (OFFSET_SEL | REGSETALL)},
26 {0xf34, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG4G | REG8G)},
27 {0x110, 0x0, 0xc0000001, (OFFSET_SEL | REGSETALL)},
28 {0x114, 0x0, 0xffffffff, (OFFSET_SEL | REGSETALL)},
29 {0x10c, 0x0, 0x00000505, REGSETALL},
30 {0x11c, 0x0, 0x00000000, REGSETALL},
31 {0x500, 0x0, 0x00000201, REGSETALL},
32 {0x514, 0x0, 0x00000100, REGSETALL},
33 {0x6a8, 0x0, 0x00040000, REGSETALL},
34 {0xea8, 0x0, 0x00040000, REGSETALL},
35 {0x504, 0x0, 0x40000000, REGSETALL}
36};
37
38static const struct ddr_reg_cfg ddr_csr_cfg1[] = {
39 {0x310, 0x0, 0x00020000, REGSETALL},
40 {0x310, 0x0, 0x00020001, REGSETALL},
41 {0x600, 0x0, 0x002e0176, REGSETALL},
42 {0x604, 0x0, 0x002e0176, REGSETALL},
43 {0x608, 0x0, 0x001700bb, REGSETALL},
44 {0x60c, 0x0, 0x000b005d, REGSETALL},
45 {0x610, 0x0, 0x0005002e, REGSETALL},
46 {0x614, 0x0, 0x00020017, REGSETALL},
47 {0x618, 0x0, 0x00020017, REGSETALL},
48 {0x61c, 0x0, 0x00020017, REGSETALL},
49 {0x678, 0x0, 0x00000019, REGSETALL},
50 {0x100, 0x0, 0x000000f8, REGSETALL},
51 {0x620, 0x0, 0x03030404, REGSETALL},
52 {0x624, 0x0, 0x04030505, REGSETALL},
53 {0x628, 0x0, 0x07030884, REGSETALL},
54 {0x62c, 0x0, 0x13150401, REGSETALL},
55 {0x630, 0x0, 0x17150604, REGSETALL},
56 {0x634, 0x0, 0x00110000, REGSETALL},
57 {0x638, 0x0, 0x200a0a08, REGSETALL},
58 {0x63c, 0x0, 0x1730f803, REGSETALL},
59 {0x640, 0x0, 0x000a0c00, REGSETALL},
60 {0x644, 0x0, 0xa005000a, REGSETALL},
61 {0x648, 0x0, 0x00000000, REGSETALL},
62 {0x64c, 0x0, 0x00081306, REGSETALL},
63 {0x650, 0x0, 0x04070304, REGSETALL},
64 {0x654, 0x0, 0x00000404, REGSETALL},
65 {0x658, 0x0, 0x00000060, REGSETALL},
66 {0x65c, 0x0, 0x00030008, REGSETALL},
67 {0x660, 0x0, 0x00000000, REGSETALL},
68 {0x680, 0x0, 0x00000603, REGSETALL},
69 {0x684, 0x0, 0x01000202, REGSETALL},
70 {0x688, 0x0, 0x0413040d, REGSETALL},
71 {0x68c, 0x0, 0x20002420, REGSETALL},
72 {0x690, 0x0, 0x00140000, REGSETALL},
73 {0x69c, 0x0, 0x01240074, REGSETALL},
74 {0x6a0, 0x0, 0x00000000, REGSETALL},
75 {0x6a4, 0x0, 0x20240c00, REGSETALL},
76 {0x6a8, 0x0, 0x00040000, REGSETALL},
77 {0x4, 0x0, 0x30010006, (F_SET | REG4G | REG8G)},
78 {0x4, 0x0, 0x10010006, (F_SET | REG2G)},
79 {0xc, 0x0, 0x00000002, REGSETALL},
80 {0x4, 0x0, 0x30020000, (F_SET | REG4G | REG8G)},
81 {0x4, 0x0, 0x10020000, (F_SET | REG2G)},
82 {0xc, 0x0, 0x00000002, REGSETALL},
83 {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
84 {0x4, 0x0, 0x10030031, (F_SET | REG2G)},
85 {0xc, 0x0, 0x00000002, REGSETALL},
86 {0x4, 0x0, 0x300b0033, (F_SET | REG4G | REG8G)},
87 {0x4, 0x0, 0x100b0033, (F_SET | REG2G)},
88 {0xc, 0x0, 0x00000002, REGSETALL},
89 {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
90 {0x4, 0x0, 0x10160016, (F_SET | REG2G)},
91 {0xc, 0x0, 0x00000002, REGSETALL},
92 {0x10, 0x0, 0x00000010, REGSETALL},
93 {0x14, 0x0, 0x00000001, REGSETALL},
94};
95
96static const struct ddr_reg_cfg ddr_csr_cfg2[] = {
97 {0xb8, 0xf0ffffff, 0x3000000, REGCLRSETALL},
98 {0x84, 0xFEFFFFFF, 0x0, REGCLRSETALL},
99 {0xb0, 0xFFFEFFFF, 0x0, REGCLRSETALL},
100 {0xb0, 0xFEFFFFFF, 0x0, REGCLRSETALL},
101 {0xb4, 0xffffffff, 0x1, REGCLRSETALL},
102 {0x248, 0xffffffff, 0x3000000, REGCLRSETALL},
103 {0x24c, 0xffffffff, 0x300, REGCLRSETALL},
104 {0x24c, 0xffffffff, 0x3000000, REGCLRSETALL},
105 {0xb0, 0xffffffff, 0x100, REGCLRSETALL},
106 {0xb8, 0xFFF0FFFF, 0x30000, REGCLRSETALL},
107 {0x84, 0xFFFEFFFF, 0x0, REGCLRSETALL},
108 {0xac, 0xFFFEFFFF, 0x0, REGCLRSETALL},
109 {0xac, 0xFEFFFFFF, 0x0, REGCLRSETALL},
110 {0xb0, 0xffffffff, 0x1, REGCLRSETALL},
111 {0x248, 0xffffffff, 0x30000, REGCLRSETALL},
112 {0x24c, 0xffffffff, 0x3, REGCLRSETALL},
113 {0x24c, 0xffffffff, 0x30000, REGCLRSETALL},
114 {0x250, 0xffffffff, 0x3000000, REGCLRSETALL},
115 {0x254, 0xffffffff, 0x3000000, REGCLRSETALL},
116 {0x258, 0xffffffff, 0x3000000, REGCLRSETALL},
117 {0xac, 0xffffffff, 0x100, REGCLRSETALL},
118 {0x10c, 0xFFFFF0FF, 0x300, REGCLRSETALL},
119 {0x110, 0xFFFFFEFF, 0x0, REGCLRSETALL},
120 {0x11c, 0xFFFEFFFF, 0x0, REGCLRSETALL},
121 {0x11c, 0xFEFFFFFF, 0x0, REGCLRSETALL},
122 {0x120, 0xffffffff, 0x100, REGCLRSETALL},
123 {0x2d0, 0xffffffff, 0x300, REGCLRSETALL},
124 {0x2dc, 0xffffffff, 0x300, REGCLRSETALL},
125 {0x2e8, 0xffffffff, 0x300, REGCLRSETALL},
126};
127
128static const struct ddr_reg_cfg ddr_csr_cfg3[] = {
129 {0x100, 0x0, 0x000000e0, REGSETALL},
130 {0x620, 0x0, 0x04041417, REGSETALL},
131 {0x624, 0x0, 0x09110609, REGSETALL},
132 {0x628, 0x0, 0x442d0994, REGSETALL},
133 {0x62c, 0x0, 0x271e102b, REGSETALL},
134 {0x630, 0x0, 0x291b140a, REGSETALL},
135 {0x634, 0x0, 0x001c0000, REGSETALL},
136 {0x638, 0x0, 0x200f0f08, REGSETALL},
137 {0x63c, 0x0, 0x29420a06, REGSETALL},
138 {0x640, 0x0, 0x019e1fc1, REGSETALL},
139 {0x644, 0x0, 0x10cb0196, REGSETALL},
140 {0x648, 0x0, 0x00000000, REGSETALL},
141 {0x64c, 0x0, 0x00082714, REGSETALL},
142 {0x650, 0x0, 0x16442f0d, REGSETALL},
143 {0x654, 0x0, 0x00001916, REGSETALL},
144 {0x658, 0x0, 0x00000060, REGSETALL},
145 {0x65c, 0x0, 0x00600020, REGSETALL},
146 {0x660, 0x0, 0x00000000, REGSETALL},
147 {0x680, 0x0, 0x0c00040f, REGSETALL},
148 {0x684, 0x0, 0x03000604, REGSETALL},
149 {0x688, 0x0, 0x0515040d, REGSETALL},
150 {0x68c, 0x0, 0x20002c20, REGSETALL},
151 {0x690, 0x0, 0x00140000, REGSETALL},
152 {0x69c, 0x0, 0x01240074, REGSETALL},
153 {0x6a0, 0x0, 0x00000000, REGSETALL},
154 {0x6a4, 0x0, 0x202c0c00, REGSETALL},
155 {0x6a8, 0x0, 0x00040000, REGSETALL},
156 {0x4, 0x0, 0x30010036, (F_SET | REG4G | REG8G)},
157 {0x4, 0x0, 0x10010036, (F_SET | REG2G)},
158 {0xc, 0x0, 0x00000002, REGSETALL},
159 {0x4, 0x0, 0x3002001b, (F_SET | REG4G | REG8G)},
160 {0x4, 0x0, 0x10010036, (F_SET | REG2G)},
161 {0xc, 0x0, 0x00000002, REGSETALL},
162 {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
163 {0x4, 0x0, 0x10030031, (F_SET | REG2G)},
164 {0xc, 0x0, 0x00000002, REGSETALL},
165 {0x4, 0x0, 0x300b0066, (F_SET | REG4G)},
166 {0x4, 0x0, 0x300b0036, (F_SET | REG8G)},
167 {0x4, 0x0, 0x100b0066, (F_SET | REG2G)},
168 {0xc, 0x0, 0x00000002, REGSETALL},
169 {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
170 {0x4, 0x0, 0x10160016, (F_SET | REG2G)},
171 {0xc, 0x0, 0x00000002, REGSETALL},
172 {0x410, 0x0, 0x00101010, REGSETALL},
173 {0x420, 0x0, 0x0c181006, REGSETALL},
174 {0x424, 0x0, 0x20200820, REGSETALL},
175 {0x428, 0x0, 0x80000020, REGSETALL},
176 {0x0, 0x0, 0x00000001, REGSETALL},
177 {0x108, 0x0, 0x00003000, REGSETALL},
178 {0x704, 0x0, 0x00000007, REGSETALL | OFFSET_SEL},
179 {0x330, 0x0, 0x09313fff, (F_SET | REG4G | REG8G)},
180 {0x330, 0x0, 0x09311fff, (F_SET | REG2G)},
181 {0x508, 0x0, 0x00000033, (F_SET | REG4G | REG8G)},
182 {0x508, 0x0, 0x00000013, (F_SET | REG2G)},
183 {0x324, 0x0, 0x00002000, REGSETALL},
184 {0x104, 0x0, 0x90000000, REGSETALL},
185 {0x510, 0x0, 0x00000100, REGSETALL},
186 {0x514, 0x0, 0x00000000, REGSETALL},
187 {0x700, 0x0, 0x00000003, REGSETALL | OFFSET_SEL},
188 {0x514, 0x0, 0x00000600, REGSETALL},
189 {0x20, 0x0, 0x00000001, REGSETALL},
190};
191
192static void ddr_csr_set(u32 *csrreg, u32 *secreg, const struct ddr_reg_cfg *data,
193 u32 len, u32 mask)
194{
195 u32 *addr;
196 u32 i;
197
198 for (i = 0; i < len; i++) {
199 if (!(data[i].flag & mask))
200 continue;
201
202 if (data[i].flag & OFFSET_SEL)
203 addr = secreg + REGOFFSET(data[i].offset);
204 else
205 addr = csrreg + REGOFFSET(data[i].offset);
206
207 if (data[i].flag & F_CLRSET)
208 DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
209 else
210 out_le32(addr, data[i].val);
211 }
212}
213
214void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
215{
216 u32 len;
217 u32 val;
218 u32 mask;
219 int ret;
220
221 switch (size) {
222 case DDR_SIZE_2G:
223 mask = REG2G;
224 break;
225
226 case DDR_SIZE_4G:
227 mask = REG4G;
228 break;
229
230 case DDR_SIZE_8G:
231 mask = REG8G;
232 break;
233
234 case DDR_SIZE_16G:
235 default:
236 return;
237 };
238
239 len = ARRAY_SIZE(ddr_csr_cfg);
240 ddr_csr_set(csrreg, secreg, ddr_csr_cfg, len, mask);
241
242 ret = wait_for_bit_le32(csrreg + REGOFFSET(0x504), BIT(31),
243 true, 1000, false);
244 if (ret)
245 return;
246
247 out_le32(csrreg + REGOFFSET(0x504), 0x0);
248 out_le32(csrreg + REGOFFSET(0x50c), 0x0);
249 udelay(300);
250 out_le32(csrreg + REGOFFSET(0x50c), 0x1);
251 mdelay(3);
252
253 switch (size) {
254 case DDR_SIZE_2G:
255 out_le32(csrreg + REGOFFSET(0x10), 0x1c);
256 break;
257
258 case DDR_SIZE_8G:
259 case DDR_SIZE_4G:
260 out_le32(csrreg + REGOFFSET(0x10), 0x3c);
261 break;
262
263 case DDR_SIZE_16G:
264 default:
265 break;
266 };
267
268 out_le32(csrreg + REGOFFSET(0x14), 0x1);
269 udelay(4);
270
271 len = ARRAY_SIZE(ddr_csr_cfg1);
272 ddr_csr_set(csrreg, secreg, ddr_csr_cfg1, len, mask);
273
274 udelay(4);
275 out_le32(csrreg + REGOFFSET(0x10), 0x11);
276 out_le32(csrreg + REGOFFSET(0x14), 0x1);
277
278 switch (size) {
279 case DDR_SIZE_4G:
280 case DDR_SIZE_8G:
281 out_le32(csrreg + REGOFFSET(0x10), 0x20);
282 out_le32(csrreg + REGOFFSET(0x14), 0x1);
283 udelay(4);
284 out_le32(csrreg + REGOFFSET(0x10), 0x21);
285 out_le32(csrreg + REGOFFSET(0x14), 0x1);
286 break;
287
288 case DDR_SIZE_2G:
289 case DDR_SIZE_16G:
290 default:
291 break;
292 };
293
294 out_le32(csrreg + REGOFFSET(0x514), 0x0);
295 ret = wait_for_bit_le32(csrreg + REGOFFSET(0x518), BIT(1),
296 true, 1000, false);
297 if (ret)
298 return;
299
300 val = in_le32(csrreg + REGOFFSET(0x518));
301 while ((val & 0x2) != 0x0) {
302 val = in_le32(phyreg + 1);
303
304 if ((val & 0x20) == 0x20) {
305 switch (val & 0x1f) {
306 case 0: /* ddrc_clock=12M */
307 DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
308 break;
309 case 1: /* ddrc_clock=200M */
310 DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV8);
311 break;
312 case 2: /* ddrc_clock=800M */
313 DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2);
314 break;
315 default:
316 break;
317 };
318
319 out_le32(phyreg + 2, 0x1);
320 ret = wait_for_bit_le32(phyreg + 2, BIT(0), false, 1000, false);
321 if (ret)
322 return;
323 }
324
325 udelay(1);
326 val = in_le32(csrreg + REGOFFSET(0x518));
327 };
328
329 val = in_le32(phyreg + 2048 + 83);
330 val = in_le32(phyreg + 2048 + 84);
331 out_le32(phyreg + 2048 + 84, val & 0xF8000000);
332
333 len = ARRAY_SIZE(ddr_csr_cfg2);
334 ddr_csr_set(phyreg + PHY_BASE_ADDR, secreg, ddr_csr_cfg2, len, mask);
335
336 len = ARRAY_SIZE(ddr_csr_cfg3);
337 ddr_csr_set(csrreg, secreg, ddr_csr_cfg3, len, mask);
338}