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git01.mediatek.com / filogic / uboot / 1d52512b2e81dbfae2cf11f6ef886bc22a7cd4d8 / . / drivers / pinctrl / renesas / pfc-r8a7792.c
blob: 7c1e6d407492852f67798339456226a40497af5a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2/*
3 * r8a7792 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]7 */
8
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]9#include <dm.h>
10#include <errno.h>
11#include <dm/pinctrl.h>
12#include <linux/kernel.h>
13
14#include "sh_pfc.h"
15
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]16#define CPU_ALL_GP(fn, sfx) \
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]17 PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
28 PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
29
30#define CPU_ALL_NOGP(fn) \
31 PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
32 PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
33 PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
34 PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
35 PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
36 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
37 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
38 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
39 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]40
41enum {
42 PINMUX_RESERVED = 0,
43
44 PINMUX_DATA_BEGIN,
45 GP_ALL(DATA),
46 PINMUX_DATA_END,
47
48 PINMUX_FUNCTION_BEGIN,
49 GP_ALL(FN),
50
51 /* GPSR0 */
52 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
53 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
54 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
55 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
56 FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
57 FN_IP1_3, FN_IP1_4,
58
59 /* GPSR1 */
60 FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
61 FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
62 FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
63 FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
64 FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
65 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
66
67 /* GPSR2 */
68 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
69 FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
70 FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
71 FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
72
73 /* GPSR3 */
74 FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
75 FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
76 FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
77 FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
78 FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
79
80 /* GPSR4 */
81 FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
82 FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
83 FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
84 FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
85 FN_VI0_FIELD,
86
87 /* GPSR5 */
88 FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
89 FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
90 FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
91 FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
92 FN_VI1_FIELD,
93
94 /* GPSR6 */
95 FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
96 FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
97 FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
98
99 /* GPSR7 */
100 FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
101 FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
102 FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
103
104 /* GPSR8 */
105 FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
106 FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
107 FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
108
109 /* GPSR9 */
110 FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
111 FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
112 FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
113
114 /* GPSR10 */
115 FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
116 FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
117 FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
118 FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
119 FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
120 FN_CAN1_TX, FN_CAN1_RX,
121
122 /* GPSR11 */
123 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
124 FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
125 FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
126 FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
127 FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
128 FN_ADICHS2, FN_AVS1, FN_AVS2,
129
130 /* IPSR0 */
131 FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
132 FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
133 FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
134 FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
135 FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
136 FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
137 FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
138 FN_DU0_DB7_C5,
139
140 /* IPSR1 */
141 FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
142 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
143 FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
144 FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
145 FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
146 FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
147 FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
148 FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
149
150 /* IPSR2 */
151 FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
152 FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
153 FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
154 FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
155 FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
156 FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
157 FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
158 FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
159 FN_VI2_FIELD, FN_AVB_TXD2,
160
161 /* IPSR3 */
162 FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
163 FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
164 FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
165 FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
166 FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
167 FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
168 FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
169 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
170
171 /* IPSR4 */
172 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
173 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
174 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
175 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
176 FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
177 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
178 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
179 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
180 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
181 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
182 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
183 FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
184 FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
185
186 /* IPSR5 */
187 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
188 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
189 FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
190 FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
191 FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
192 FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
193
194 /* IPSR6 */
195 FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
196 FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
197 FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
198 FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
199 FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
200 FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
201
202 /* IPSR7 */
203 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
204 FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
205 FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
206 FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
207 FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
208 FN_AUDIO_CLKA, FN_AUDIO_CLKB,
209
210 /* MOD_SEL */
211 FN_SEL_VI1_0, FN_SEL_VI1_1,
212 PINMUX_FUNCTION_END,
213
214 PINMUX_MARK_BEGIN,
215 DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
216 DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
217 DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
218 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
219 DU1_DISP_MARK, DU1_CDE_MARK,
220
221 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
222 D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
223 D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
224 A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
225 A12_MARK, A13_MARK, A14_MARK, A15_MARK,
226
227 A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
228 EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
229 EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
230 WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
231 IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
232
233 VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
234 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
235 VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
236 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
237 VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
238 VI0_FIELD_MARK,
239
240 VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
241 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
242 VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
243 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
244 VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
245 VI1_FIELD_MARK,
246
247 VI3_D10_Y2_MARK, VI3_FIELD_MARK,
248
249 VI4_CLK_MARK,
250
251 VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
252 VI5_FIELD_MARK,
253
254 HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
255 TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
256 TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
257 CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
258
259 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
260 SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
261 ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
262 ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
263
264 /* IPSR0 */
265 DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
266 DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
267 DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
268 DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
269 DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
270 DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
271 DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
272 DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
273
274 /* IPSR1 */
275 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
276 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
277 DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
278 DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
279 DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
280 DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
281 A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
282 A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
283
284 /* IPSR2 */
285 VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
286 VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
287 VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
288 VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
289 VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
290 VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
291 VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
292 VI2_D10_Y2_MARK, AVB_TXD0_MARK,
293 VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
294
295 /* IPSR3 */
296 VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
297 VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
298 VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
299 VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
300 VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
301 VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
302 VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
303 VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
304
305 /* IPSR4 */
306 VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
307 VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
308 RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
309 VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
310 VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
311 VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
312 VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
313 VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
314 VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
315 VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
316 VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
317
318 /* IPSR5 */
319 VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
320 VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
321 VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
322 VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
323 VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
324 VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
325 VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
326
327 /* IPSR6 */
328 MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
329 MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
330 MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
331 MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
332 DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
333 RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
334 RX3_MARK,
335
336 /* IPSR7 */
337 PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
338 FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
339 PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
340 SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
341 SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
342 AUDIO_CLKB_MARK,
343 PINMUX_MARK_END,
344};
345
346static const u16 pinmux_data[] = {
347 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
348
349 PINMUX_SINGLE(DU1_DB2_C0_DATA12),
350 PINMUX_SINGLE(DU1_DB3_C1_DATA13),
351 PINMUX_SINGLE(DU1_DB4_C2_DATA14),
352 PINMUX_SINGLE(DU1_DB5_C3_DATA15),
353 PINMUX_SINGLE(DU1_DB6_C4),
354 PINMUX_SINGLE(DU1_DB7_C5),
355 PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
356 PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
357 PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
358 PINMUX_SINGLE(DU1_DISP),
359 PINMUX_SINGLE(DU1_CDE),
360 PINMUX_SINGLE(D0),
361 PINMUX_SINGLE(D1),
362 PINMUX_SINGLE(D2),
363 PINMUX_SINGLE(D3),
364 PINMUX_SINGLE(D4),
365 PINMUX_SINGLE(D5),
366 PINMUX_SINGLE(D6),
367 PINMUX_SINGLE(D7),
368 PINMUX_SINGLE(D8),
369 PINMUX_SINGLE(D9),
370 PINMUX_SINGLE(D10),
371 PINMUX_SINGLE(D11),
372 PINMUX_SINGLE(D12),
373 PINMUX_SINGLE(D13),
374 PINMUX_SINGLE(D14),
375 PINMUX_SINGLE(D15),
376 PINMUX_SINGLE(A0),
377 PINMUX_SINGLE(A1),
378 PINMUX_SINGLE(A2),
379 PINMUX_SINGLE(A3),
380 PINMUX_SINGLE(A4),
381 PINMUX_SINGLE(A5),
382 PINMUX_SINGLE(A6),
383 PINMUX_SINGLE(A7),
384 PINMUX_SINGLE(A8),
385 PINMUX_SINGLE(A9),
386 PINMUX_SINGLE(A10),
387 PINMUX_SINGLE(A11),
388 PINMUX_SINGLE(A12),
389 PINMUX_SINGLE(A13),
390 PINMUX_SINGLE(A14),
391 PINMUX_SINGLE(A15),
392 PINMUX_SINGLE(A16),
393 PINMUX_SINGLE(A17),
394 PINMUX_SINGLE(A18),
395 PINMUX_SINGLE(A19),
396 PINMUX_SINGLE(CS1_N_A26),
397 PINMUX_SINGLE(EX_CS0_N),
398 PINMUX_SINGLE(EX_CS1_N),
399 PINMUX_SINGLE(EX_CS2_N),
400 PINMUX_SINGLE(EX_CS3_N),
401 PINMUX_SINGLE(EX_CS4_N),
402 PINMUX_SINGLE(EX_CS5_N),
403 PINMUX_SINGLE(BS_N),
404 PINMUX_SINGLE(RD_N),
405 PINMUX_SINGLE(RD_WR_N),
406 PINMUX_SINGLE(WE0_N),
407 PINMUX_SINGLE(WE1_N),
408 PINMUX_SINGLE(EX_WAIT0),
409 PINMUX_SINGLE(IRQ0),
410 PINMUX_SINGLE(IRQ1),
411 PINMUX_SINGLE(IRQ2),
412 PINMUX_SINGLE(IRQ3),
413 PINMUX_SINGLE(CS0_N),
414 PINMUX_SINGLE(VI0_CLK),
415 PINMUX_SINGLE(VI0_CLKENB),
416 PINMUX_SINGLE(VI0_HSYNC_N),
417 PINMUX_SINGLE(VI0_VSYNC_N),
418 PINMUX_SINGLE(VI0_D0_B0_C0),
419 PINMUX_SINGLE(VI0_D1_B1_C1),
420 PINMUX_SINGLE(VI0_D2_B2_C2),
421 PINMUX_SINGLE(VI0_D3_B3_C3),
422 PINMUX_SINGLE(VI0_D4_B4_C4),
423 PINMUX_SINGLE(VI0_D5_B5_C5),
424 PINMUX_SINGLE(VI0_D6_B6_C6),
425 PINMUX_SINGLE(VI0_D7_B7_C7),
426 PINMUX_SINGLE(VI0_D8_G0_Y0),
427 PINMUX_SINGLE(VI0_D9_G1_Y1),
428 PINMUX_SINGLE(VI0_D10_G2_Y2),
429 PINMUX_SINGLE(VI0_D11_G3_Y3),
430 PINMUX_SINGLE(VI0_FIELD),
431 PINMUX_SINGLE(VI1_CLK),
432 PINMUX_SINGLE(VI1_CLKENB),
433 PINMUX_SINGLE(VI1_HSYNC_N),
434 PINMUX_SINGLE(VI1_VSYNC_N),
435 PINMUX_SINGLE(VI1_D0_B0_C0),
436 PINMUX_SINGLE(VI1_D1_B1_C1),
437 PINMUX_SINGLE(VI1_D2_B2_C2),
438 PINMUX_SINGLE(VI1_D3_B3_C3),
439 PINMUX_SINGLE(VI1_D4_B4_C4),
440 PINMUX_SINGLE(VI1_D5_B5_C5),
441 PINMUX_SINGLE(VI1_D6_B6_C6),
442 PINMUX_SINGLE(VI1_D7_B7_C7),
443 PINMUX_SINGLE(VI1_D8_G0_Y0),
444 PINMUX_SINGLE(VI1_D9_G1_Y1),
445 PINMUX_SINGLE(VI1_D10_G2_Y2),
446 PINMUX_SINGLE(VI1_D11_G3_Y3),
447 PINMUX_SINGLE(VI1_FIELD),
448 PINMUX_SINGLE(VI3_D10_Y2),
449 PINMUX_SINGLE(VI3_FIELD),
450 PINMUX_SINGLE(VI4_CLK),
451 PINMUX_SINGLE(VI5_CLK),
452 PINMUX_SINGLE(VI5_D9_Y1),
453 PINMUX_SINGLE(VI5_D10_Y2),
454 PINMUX_SINGLE(VI5_D11_Y3),
455 PINMUX_SINGLE(VI5_FIELD),
456 PINMUX_SINGLE(HRTS0_N),
457 PINMUX_SINGLE(HCTS1_N),
458 PINMUX_SINGLE(SCK0),
459 PINMUX_SINGLE(CTS0_N),
460 PINMUX_SINGLE(RTS0_N),
461 PINMUX_SINGLE(TX0),
462 PINMUX_SINGLE(RX0),
463 PINMUX_SINGLE(SCK1),
464 PINMUX_SINGLE(CTS1_N),
465 PINMUX_SINGLE(RTS1_N),
466 PINMUX_SINGLE(TX1),
467 PINMUX_SINGLE(RX1),
468 PINMUX_SINGLE(SCIF_CLK),
469 PINMUX_SINGLE(CAN0_TX),
470 PINMUX_SINGLE(CAN0_RX),
471 PINMUX_SINGLE(CAN_CLK),
472 PINMUX_SINGLE(CAN1_TX),
473 PINMUX_SINGLE(CAN1_RX),
474 PINMUX_SINGLE(SD0_CLK),
475 PINMUX_SINGLE(SD0_CMD),
476 PINMUX_SINGLE(SD0_DAT0),
477 PINMUX_SINGLE(SD0_DAT1),
478 PINMUX_SINGLE(SD0_DAT2),
479 PINMUX_SINGLE(SD0_DAT3),
480 PINMUX_SINGLE(SD0_CD),
481 PINMUX_SINGLE(SD0_WP),
482 PINMUX_SINGLE(ADICLK),
483 PINMUX_SINGLE(ADICS_SAMP),
484 PINMUX_SINGLE(ADIDATA),
485 PINMUX_SINGLE(ADICHS0),
486 PINMUX_SINGLE(ADICHS1),
487 PINMUX_SINGLE(ADICHS2),
488 PINMUX_SINGLE(AVS1),
489 PINMUX_SINGLE(AVS2),
490
491 /* IPSR0 */
492 PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
493 PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
494 PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
495 PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
496 PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
497 PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
498 PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
499 PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
500 PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
501 PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
502 PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
503 PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
504 PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
505 PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
506 PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
507 PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
508 PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
509 PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
510 PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
511 PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
512 PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
513 PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
514 PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
515 PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
516
517 /* IPSR1 */
518 PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
519 PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
520 PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
521 PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
522 PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
523 PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
524 PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
525 PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
526 PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
527 PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
528 PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
529 PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
530 PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
531 PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
532 PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
533 PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
534 PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
535 PINMUX_IPSR_GPSR(IP1_17, A20),
536 PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
537 PINMUX_IPSR_GPSR(IP1_18, A21),
538 PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
539 PINMUX_IPSR_GPSR(IP1_19, A22),
540 PINMUX_IPSR_GPSR(IP1_19, IO2),
541 PINMUX_IPSR_GPSR(IP1_20, A23),
542 PINMUX_IPSR_GPSR(IP1_20, IO3),
543 PINMUX_IPSR_GPSR(IP1_21, A24),
544 PINMUX_IPSR_GPSR(IP1_21, SPCLK),
545 PINMUX_IPSR_GPSR(IP1_22, A25),
546 PINMUX_IPSR_GPSR(IP1_22, SSL),
547
548 /* IPSR2 */
549 PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
550 PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
551 PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
552 PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
553 PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
554 PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
555 PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
556 PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
557 PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
558 PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
559 PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
560 PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
561 PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
562 PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
563 PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
564 PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
565 PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
566 PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
567 PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
568 PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
569 PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
570 PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
571 PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
572 PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
573 PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
574 PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
575 PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
576 PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
577 PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
578 PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
579 PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
580 PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
581 PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
582 PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
583
584 /* IPSR3 */
585 PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
586 PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
587 PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
588 PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
589 PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
590 PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
591 PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
592 PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
593 PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
594 PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
595 PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
596 PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
597 PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
598 PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
599 PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
600 PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
601 PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
602 PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
603 PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
604 PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
605 PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
606 PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
607 PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
608 PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
609 PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
610 PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
611 PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
612 PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
613 PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
614 PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
615
616 /* IPSR4 */
617 PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
618 PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
619 PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
620 PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
621 PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
622 PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
623 PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
624 PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
625 PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
626 PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
627 PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
628 PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
629 PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
630 PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
631 PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
632 PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
633 PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
634 PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
635 PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
636 PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
637 PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
638 PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
639 PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
640 PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
641 PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
642 PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
643 PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
644 PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
645 PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
646 PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
647 PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
648 PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
649 PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
650 PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
651 PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
652 PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
653 PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
654 PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
655 PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
656 PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
657
658 /* IPSR5 */
659 PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
660 PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
661 PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
662 PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
663 PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
664 PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
665 PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
666 PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
667 PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
668 PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
669 PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
670 PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
671 PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
672 PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
673 PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
674 PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
675 PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
676 PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
677 PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
678 PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
679 PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
680 PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
681 PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
682 PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
683
684 /* IPSR6 */
685 PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
686 PINMUX_IPSR_GPSR(IP6_0, HSCK0),
687 PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
688 PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
689 PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
690 PINMUX_IPSR_GPSR(IP6_2, HTX0),
691 PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
692 PINMUX_IPSR_GPSR(IP6_3, HRX0),
693 PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
694 PINMUX_IPSR_GPSR(IP6_4, HSCK1),
695 PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
696 PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
697 PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
698 PINMUX_IPSR_GPSR(IP6_6, HTX1),
699 PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
700 PINMUX_IPSR_GPSR(IP6_7, HRX1),
701 PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
702 PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
703 PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
704 PINMUX_IPSR_GPSR(IP6_11_10, TX2),
705 PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
706 PINMUX_IPSR_GPSR(IP6_13_12, RX2),
707 PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
708 PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
709 PINMUX_IPSR_GPSR(IP6_16, TX3),
710 PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
711 PINMUX_IPSR_GPSR(IP6_18_17, RX3),
712
713 /* IPSR7 */
714 PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
715 PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
716 PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
717 PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
718 PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
719 PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
720 PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
721 PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
722 PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
723 PINMUX_IPSR_GPSR(IP7_6, PWM3),
724 PINMUX_IPSR_GPSR(IP7_7, PWM4),
725 PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
726 PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
727 PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
728 PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
729 PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
730 PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
731 PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
732 PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
733 PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
734 PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
735 PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
736 PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
737 PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
738};
739
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]740/*
741 * Pins not associated with a GPIO port.
742 */
743enum {
744 GP_ASSIGN_LAST(),
745 NOGP_ALL(),
746};
747
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]748static const struct sh_pfc_pin pinmux_pins[] = {
749 PINMUX_GPIO_GP_ALL(),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]750 PINMUX_NOGP_ALL(),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]751};
752
753/* - AVB -------------------------------------------------------------------- */
754static const unsigned int avb_link_pins[] = {
755 RCAR_GP_PIN(7, 9),
756};
757static const unsigned int avb_link_mux[] = {
758 AVB_LINK_MARK,
759};
760static const unsigned int avb_magic_pins[] = {
761 RCAR_GP_PIN(7, 10),
762};
763static const unsigned int avb_magic_mux[] = {
764 AVB_MAGIC_MARK,
765};
766static const unsigned int avb_phy_int_pins[] = {
767 RCAR_GP_PIN(7, 11),
768};
769static const unsigned int avb_phy_int_mux[] = {
770 AVB_PHY_INT_MARK,
771};
772static const unsigned int avb_mdio_pins[] = {
773 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
774};
775static const unsigned int avb_mdio_mux[] = {
776 AVB_MDC_MARK, AVB_MDIO_MARK,
777};
778static const unsigned int avb_mii_pins[] = {
779 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
780 RCAR_GP_PIN(6, 12),
781
782 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
783 RCAR_GP_PIN(6, 5),
784
785 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
786 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
787 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),
788};
789static const unsigned int avb_mii_mux[] = {
790 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
791 AVB_TXD3_MARK,
792
793 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
794 AVB_RXD3_MARK,
795
796 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
797 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
798 AVB_TX_CLK_MARK, AVB_COL_MARK,
799};
800static const unsigned int avb_gmii_pins[] = {
801 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
802 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2),
803 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
804
805 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
806 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
807 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
808
809 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
810 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
811 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
812 RCAR_GP_PIN(6, 11),
813};
814static const unsigned int avb_gmii_mux[] = {
815 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
816 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
817 AVB_TXD6_MARK, AVB_TXD7_MARK,
818
819 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
820 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
821 AVB_RXD6_MARK, AVB_RXD7_MARK,
822
823 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
824 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
825 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
826 AVB_COL_MARK,
827};
828static const unsigned int avb_avtp_match_pins[] = {
829 RCAR_GP_PIN(7, 15),
830};
831static const unsigned int avb_avtp_match_mux[] = {
832 AVB_AVTP_MATCH_MARK,
833};
834/* - CAN -------------------------------------------------------------------- */
835static const unsigned int can0_data_pins[] = {
836 /* TX, RX */
837 RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
838};
839static const unsigned int can0_data_mux[] = {
840 CAN0_TX_MARK, CAN0_RX_MARK,
841};
842static const unsigned int can1_data_pins[] = {
843 /* TX, RX */
844 RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
845};
846static const unsigned int can1_data_mux[] = {
847 CAN1_TX_MARK, CAN1_RX_MARK,
848};
849static const unsigned int can_clk_pins[] = {
850 /* CAN_CLK */
851 RCAR_GP_PIN(10, 29),
852};
853static const unsigned int can_clk_mux[] = {
854 CAN_CLK_MARK,
855};
856/* - DU --------------------------------------------------------------------- */
857static const unsigned int du0_rgb666_pins[] = {
858 /* R[7:2], G[7:2], B[7:2] */
859 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
860 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
861 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
862 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
863 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
864 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
865};
866static const unsigned int du0_rgb666_mux[] = {
867 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
868 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
869 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
870 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
871 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
872 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
873};
874static const unsigned int du0_rgb888_pins[] = {
875 /* R[7:0], G[7:0], B[7:0] */
876 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
877 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
878 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
879 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
880 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
881 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
882 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
883 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
884 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
885};
886static const unsigned int du0_rgb888_mux[] = {
887 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
888 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
889 DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
890 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
891 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
892 DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
893 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
894 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
895 DU0_DB1_MARK, DU0_DB0_MARK,
896};
897static const unsigned int du0_sync_pins[] = {
898 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
899 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
900};
901static const unsigned int du0_sync_mux[] = {
902 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
903};
904static const unsigned int du0_oddf_pins[] = {
905 /* EXODDF/ODDF/DISP/CDE */
906 RCAR_GP_PIN(0, 26),
907};
908static const unsigned int du0_oddf_mux[] = {
909 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
910};
911static const unsigned int du0_disp_pins[] = {
912 /* DISP */
913 RCAR_GP_PIN(0, 27),
914};
915static const unsigned int du0_disp_mux[] = {
916 DU0_DISP_MARK,
917};
918static const unsigned int du0_cde_pins[] = {
919 /* CDE */
920 RCAR_GP_PIN(0, 28),
921};
922static const unsigned int du0_cde_mux[] = {
923 DU0_CDE_MARK,
924};
925static const unsigned int du1_rgb666_pins[] = {
926 /* R[7:2], G[7:2], B[7:2] */
927 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
928 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
929 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
930 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
931 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
932 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
933};
934static const unsigned int du1_rgb666_mux[] = {
935 DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
936 DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
937 DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
938 DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
939 DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
940 DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
941};
942static const unsigned int du1_sync_pins[] = {
943 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
944 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
945};
946static const unsigned int du1_sync_mux[] = {
947 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
948};
949static const unsigned int du1_oddf_pins[] = {
950 /* EXODDF/ODDF/DISP/CDE */
951 RCAR_GP_PIN(1, 20),
952};
953static const unsigned int du1_oddf_mux[] = {
954 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
955};
956static const unsigned int du1_disp_pins[] = {
957 /* DISP */
958 RCAR_GP_PIN(1, 21),
959};
960static const unsigned int du1_disp_mux[] = {
961 DU1_DISP_MARK,
962};
963static const unsigned int du1_cde_pins[] = {
964 /* CDE */
965 RCAR_GP_PIN(1, 22),
966};
967static const unsigned int du1_cde_mux[] = {
968 DU1_CDE_MARK,
969};
970/* - INTC ------------------------------------------------------------------- */
971static const unsigned int intc_irq0_pins[] = {
972 /* IRQ0 */
973 RCAR_GP_PIN(3, 19),
974};
975static const unsigned int intc_irq0_mux[] = {
976 IRQ0_MARK,
977};
978static const unsigned int intc_irq1_pins[] = {
979 /* IRQ1 */
980 RCAR_GP_PIN(3, 20),
981};
982static const unsigned int intc_irq1_mux[] = {
983 IRQ1_MARK,
984};
985static const unsigned int intc_irq2_pins[] = {
986 /* IRQ2 */
987 RCAR_GP_PIN(3, 21),
988};
989static const unsigned int intc_irq2_mux[] = {
990 IRQ2_MARK,
991};
992static const unsigned int intc_irq3_pins[] = {
993 /* IRQ3 */
994 RCAR_GP_PIN(3, 22),
995};
996static const unsigned int intc_irq3_mux[] = {
997 IRQ3_MARK,
998};
999/* - LBSC ------------------------------------------------------------------- */
1000static const unsigned int lbsc_cs0_pins[] = {
1001 /* CS0# */
1002 RCAR_GP_PIN(3, 27),
1003};
1004static const unsigned int lbsc_cs0_mux[] = {
1005 CS0_N_MARK,
1006};
1007static const unsigned int lbsc_cs1_pins[] = {
1008 /* CS1#_A26 */
1009 RCAR_GP_PIN(3, 6),
1010};
1011static const unsigned int lbsc_cs1_mux[] = {
1012 CS1_N_A26_MARK,
1013};
1014static const unsigned int lbsc_ex_cs0_pins[] = {
1015 /* EX_CS0# */
1016 RCAR_GP_PIN(3, 7),
1017};
1018static const unsigned int lbsc_ex_cs0_mux[] = {
1019 EX_CS0_N_MARK,
1020};
1021static const unsigned int lbsc_ex_cs1_pins[] = {
1022 /* EX_CS1# */
1023 RCAR_GP_PIN(3, 8),
1024};
1025static const unsigned int lbsc_ex_cs1_mux[] = {
1026 EX_CS1_N_MARK,
1027};
1028static const unsigned int lbsc_ex_cs2_pins[] = {
1029 /* EX_CS2# */
1030 RCAR_GP_PIN(3, 9),
1031};
1032static const unsigned int lbsc_ex_cs2_mux[] = {
1033 EX_CS2_N_MARK,
1034};
1035static const unsigned int lbsc_ex_cs3_pins[] = {
1036 /* EX_CS3# */
1037 RCAR_GP_PIN(3, 10),
1038};
1039static const unsigned int lbsc_ex_cs3_mux[] = {
1040 EX_CS3_N_MARK,
1041};
1042static const unsigned int lbsc_ex_cs4_pins[] = {
1043 /* EX_CS4# */
1044 RCAR_GP_PIN(3, 11),
1045};
1046static const unsigned int lbsc_ex_cs4_mux[] = {
1047 EX_CS4_N_MARK,
1048};
1049static const unsigned int lbsc_ex_cs5_pins[] = {
1050 /* EX_CS5# */
1051 RCAR_GP_PIN(3, 12),
1052};
1053static const unsigned int lbsc_ex_cs5_mux[] = {
1054 EX_CS5_N_MARK,
1055};
1056/* - MSIOF0 ----------------------------------------------------------------- */
1057static const unsigned int msiof0_clk_pins[] = {
1058 /* SCK */
1059 RCAR_GP_PIN(10, 0),
1060};
1061static const unsigned int msiof0_clk_mux[] = {
1062 MSIOF0_SCK_MARK,
1063};
1064static const unsigned int msiof0_sync_pins[] = {
1065 /* SYNC */
1066 RCAR_GP_PIN(10, 1),
1067};
1068static const unsigned int msiof0_sync_mux[] = {
1069 MSIOF0_SYNC_MARK,
1070};
1071static const unsigned int msiof0_rx_pins[] = {
1072 /* RXD */
1073 RCAR_GP_PIN(10, 4),
1074};
1075static const unsigned int msiof0_rx_mux[] = {
1076 MSIOF0_RXD_MARK,
1077};
1078static const unsigned int msiof0_tx_pins[] = {
1079 /* TXD */
1080 RCAR_GP_PIN(10, 3),
1081};
1082static const unsigned int msiof0_tx_mux[] = {
1083 MSIOF0_TXD_MARK,
1084};
1085/* - MSIOF1 ----------------------------------------------------------------- */
1086static const unsigned int msiof1_clk_pins[] = {
1087 /* SCK */
1088 RCAR_GP_PIN(10, 5),
1089};
1090static const unsigned int msiof1_clk_mux[] = {
1091 MSIOF1_SCK_MARK,
1092};
1093static const unsigned int msiof1_sync_pins[] = {
1094 /* SYNC */
1095 RCAR_GP_PIN(10, 6),
1096};
1097static const unsigned int msiof1_sync_mux[] = {
1098 MSIOF1_SYNC_MARK,
1099};
1100static const unsigned int msiof1_rx_pins[] = {
1101 /* RXD */
1102 RCAR_GP_PIN(10, 9),
1103};
1104static const unsigned int msiof1_rx_mux[] = {
1105 MSIOF1_RXD_MARK,
1106};
1107static const unsigned int msiof1_tx_pins[] = {
1108 /* TXD */
1109 RCAR_GP_PIN(10, 8),
1110};
1111static const unsigned int msiof1_tx_mux[] = {
1112 MSIOF1_TXD_MARK,
1113};
1114/* - QSPI ------------------------------------------------------------------- */
1115static const unsigned int qspi_ctrl_pins[] = {
1116 /* SPCLK, SSL */
1117 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1118};
1119static const unsigned int qspi_ctrl_mux[] = {
1120 SPCLK_MARK, SSL_MARK,
1121};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1122static const unsigned int qspi_data_pins[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1123 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1124 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1125 RCAR_GP_PIN(3, 24),
1126};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1127static const unsigned int qspi_data_mux[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1128 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1129};
1130/* - SCIF0 ------------------------------------------------------------------ */
1131static const unsigned int scif0_data_pins[] = {
1132 /* RX, TX */
1133 RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1134};
1135static const unsigned int scif0_data_mux[] = {
1136 RX0_MARK, TX0_MARK,
1137};
1138static const unsigned int scif0_clk_pins[] = {
1139 /* SCK */
1140 RCAR_GP_PIN(10, 10),
1141};
1142static const unsigned int scif0_clk_mux[] = {
1143 SCK0_MARK,
1144};
1145static const unsigned int scif0_ctrl_pins[] = {
1146 /* RTS, CTS */
1147 RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1148};
1149static const unsigned int scif0_ctrl_mux[] = {
1150 RTS0_N_MARK, CTS0_N_MARK,
1151};
1152/* - SCIF1 ------------------------------------------------------------------ */
1153static const unsigned int scif1_data_pins[] = {
1154 /* RX, TX */
1155 RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
1156};
1157static const unsigned int scif1_data_mux[] = {
1158 RX1_MARK, TX1_MARK,
1159};
1160static const unsigned int scif1_clk_pins[] = {
1161 /* SCK */
1162 RCAR_GP_PIN(10, 15),
1163};
1164static const unsigned int scif1_clk_mux[] = {
1165 SCK1_MARK,
1166};
1167static const unsigned int scif1_ctrl_pins[] = {
1168 /* RTS, CTS */
1169 RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
1170};
1171static const unsigned int scif1_ctrl_mux[] = {
1172 RTS1_N_MARK, CTS1_N_MARK,
1173};
1174/* - SCIF2 ------------------------------------------------------------------ */
1175static const unsigned int scif2_data_pins[] = {
1176 /* RX, TX */
1177 RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
1178};
1179static const unsigned int scif2_data_mux[] = {
1180 RX2_MARK, TX2_MARK,
1181};
1182static const unsigned int scif2_clk_pins[] = {
1183 /* SCK */
1184 RCAR_GP_PIN(10, 20),
1185};
1186static const unsigned int scif2_clk_mux[] = {
1187 SCK2_MARK,
1188};
1189/* - SCIF3 ------------------------------------------------------------------ */
1190static const unsigned int scif3_data_pins[] = {
1191 /* RX, TX */
1192 RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1193};
1194static const unsigned int scif3_data_mux[] = {
1195 RX3_MARK, TX3_MARK,
1196};
1197static const unsigned int scif3_clk_pins[] = {
1198 /* SCK */
1199 RCAR_GP_PIN(10, 23),
1200};
1201static const unsigned int scif3_clk_mux[] = {
1202 SCK3_MARK,
1203};
1204/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1205static const unsigned int sdhi0_data_pins[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1206 /* DAT[0-3] */
1207 RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1208 RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1209};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1210static const unsigned int sdhi0_data_mux[] = {
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1211 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1212};
1213static const unsigned int sdhi0_ctrl_pins[] = {
1214 /* CLK, CMD */
1215 RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1216};
1217static const unsigned int sdhi0_ctrl_mux[] = {
1218 SD0_CLK_MARK, SD0_CMD_MARK,
1219};
1220static const unsigned int sdhi0_cd_pins[] = {
1221 /* CD */
1222 RCAR_GP_PIN(11, 11),
1223};
1224static const unsigned int sdhi0_cd_mux[] = {
1225 SD0_CD_MARK,
1226};
1227static const unsigned int sdhi0_wp_pins[] = {
1228 /* WP */
1229 RCAR_GP_PIN(11, 12),
1230};
1231static const unsigned int sdhi0_wp_mux[] = {
1232 SD0_WP_MARK,
1233};
1234/* - VIN0 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1235static const unsigned int vin0_data_pins[] = {
1236 /* B */
1237 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1238 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1239 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1240 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1241 /* G */
1242 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1243 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1244 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1245 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1246 /* R */
1247 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1248 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1249 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1250 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1251};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1252static const unsigned int vin0_data_mux[] = {
1253 /* B */
1254 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1255 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1256 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1257 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1258 /* G */
1259 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1260 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1261 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1262 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1263 /* R */
1264 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1265 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1266 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1267 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1268};
1269static const unsigned int vin0_data18_pins[] = {
1270 /* B */
1271 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1272 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1273 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1274 /* G */
1275 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1276 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1277 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1278 /* R */
1279 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1280 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1281 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1282};
1283static const unsigned int vin0_data18_mux[] = {
1284 /* B */
1285 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1286 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1287 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1288 /* G */
1289 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1290 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1291 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1292 /* R */
1293 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1294 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1295 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1296};
1297static const unsigned int vin0_sync_pins[] = {
1298 /* HSYNC#, VSYNC# */
1299 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1300};
1301static const unsigned int vin0_sync_mux[] = {
1302 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1303};
1304static const unsigned int vin0_field_pins[] = {
1305 RCAR_GP_PIN(4, 16),
1306};
1307static const unsigned int vin0_field_mux[] = {
1308 VI0_FIELD_MARK,
1309};
1310static const unsigned int vin0_clkenb_pins[] = {
1311 RCAR_GP_PIN(4, 1),
1312};
1313static const unsigned int vin0_clkenb_mux[] = {
1314 VI0_CLKENB_MARK,
1315};
1316static const unsigned int vin0_clk_pins[] = {
1317 RCAR_GP_PIN(4, 0),
1318};
1319static const unsigned int vin0_clk_mux[] = {
1320 VI0_CLK_MARK,
1321};
1322/* - VIN1 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1323static const unsigned int vin1_data_pins[] = {
1324 /* B */
1325 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1326 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1327 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1328 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1329 /* G */
1330 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1331 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1332 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1333 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1334 /* R */
1335 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1336 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1337 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1338 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1339};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1340static const unsigned int vin1_data_mux[] = {
1341 /* B */
1342 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1343 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1344 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1345 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1346 /* G */
1347 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1348 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1349 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1350 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1351 /* R */
1352 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1353 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1354 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1355 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1356};
1357static const unsigned int vin1_data18_pins[] = {
1358 /* B */
1359 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1360 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1361 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1362 /* G */
1363 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1364 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1365 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1366 /* R */
1367 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1368 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1369 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1370};
1371static const unsigned int vin1_data18_mux[] = {
1372 /* B */
1373 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1374 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1375 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1376 /* G */
1377 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1378 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1379 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1380 /* R */
1381 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1382 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1383 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1384};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1385static const unsigned int vin1_data_b_pins[] = {
1386 /* B */
1387 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1388 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1389 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1390 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1391 /* G */
1392 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1393 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1394 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1395 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1396 /* R */
1397 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1398 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1399 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1400 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1401};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1402static const unsigned int vin1_data_b_mux[] = {
1403 /* B */
1404 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1405 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1406 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1407 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1408 /* G */
1409 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1410 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1411 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1412 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1413 /* R */
1414 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1415 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1416 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1417 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1418};
1419static const unsigned int vin1_data18_b_pins[] = {
1420 /* B */
1421 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1422 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1423 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1424 /* G */
1425 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1426 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1427 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1428 /* R */
1429 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1430 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1431 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1432};
1433static const unsigned int vin1_data18_b_mux[] = {
1434 /* B */
1435 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1436 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1437 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1438 /* G */
1439 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1440 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1441 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1442 /* R */
1443 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1444 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1445 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1446};
1447static const unsigned int vin1_sync_pins[] = {
1448 /* HSYNC#, VSYNC# */
1449 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1450};
1451static const unsigned int vin1_sync_mux[] = {
1452 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1453};
1454static const unsigned int vin1_field_pins[] = {
1455 RCAR_GP_PIN(5, 16),
1456};
1457static const unsigned int vin1_field_mux[] = {
1458 VI1_FIELD_MARK,
1459};
1460static const unsigned int vin1_clkenb_pins[] = {
1461 RCAR_GP_PIN(5, 1),
1462};
1463static const unsigned int vin1_clkenb_mux[] = {
1464 VI1_CLKENB_MARK,
1465};
1466static const unsigned int vin1_clk_pins[] = {
1467 RCAR_GP_PIN(5, 0),
1468};
1469static const unsigned int vin1_clk_mux[] = {
1470 VI1_CLK_MARK,
1471};
1472/* - VIN2 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1473static const unsigned int vin2_data_pins[] = {
1474 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1475 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1476 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1477 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1478 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1479 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1480 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1481 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1482};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1483static const unsigned int vin2_data_mux[] = {
1484 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1485 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1486 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1487 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1488 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1489 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1490 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1491 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1492};
1493static const unsigned int vin2_sync_pins[] = {
1494 /* HSYNC#, VSYNC# */
1495 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1496};
1497static const unsigned int vin2_sync_mux[] = {
1498 VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1499};
1500static const unsigned int vin2_field_pins[] = {
1501 RCAR_GP_PIN(6, 16),
1502};
1503static const unsigned int vin2_field_mux[] = {
1504 VI2_FIELD_MARK,
1505};
1506static const unsigned int vin2_clkenb_pins[] = {
1507 RCAR_GP_PIN(6, 1),
1508};
1509static const unsigned int vin2_clkenb_mux[] = {
1510 VI2_CLKENB_MARK,
1511};
1512static const unsigned int vin2_clk_pins[] = {
1513 RCAR_GP_PIN(6, 0),
1514};
1515static const unsigned int vin2_clk_mux[] = {
1516 VI2_CLK_MARK,
1517};
1518/* - VIN3 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1519static const unsigned int vin3_data_pins[] = {
1520 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1521 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1522 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1523 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1524 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1525 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1526 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1527 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1528};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1529static const unsigned int vin3_data_mux[] = {
1530 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1531 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1532 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1533 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1534 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1535 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1536 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1537 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1538};
1539static const unsigned int vin3_sync_pins[] = {
1540 /* HSYNC#, VSYNC# */
1541 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1542};
1543static const unsigned int vin3_sync_mux[] = {
1544 VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1545};
1546static const unsigned int vin3_field_pins[] = {
1547 RCAR_GP_PIN(7, 16),
1548};
1549static const unsigned int vin3_field_mux[] = {
1550 VI3_FIELD_MARK,
1551};
1552static const unsigned int vin3_clkenb_pins[] = {
1553 RCAR_GP_PIN(7, 1),
1554};
1555static const unsigned int vin3_clkenb_mux[] = {
1556 VI3_CLKENB_MARK,
1557};
1558static const unsigned int vin3_clk_pins[] = {
1559 RCAR_GP_PIN(7, 0),
1560};
1561static const unsigned int vin3_clk_mux[] = {
1562 VI3_CLK_MARK,
1563};
1564/* - VIN4 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1565static const unsigned int vin4_data_pins[] = {
1566 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1567 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1568 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1569 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1570 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1571 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1572};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1573static const unsigned int vin4_data_mux[] = {
1574 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1575 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1576 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1577 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1578 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1579 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1580};
1581static const unsigned int vin4_sync_pins[] = {
1582 /* HSYNC#, VSYNC# */
1583 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1584};
1585static const unsigned int vin4_sync_mux[] = {
1586 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1587};
1588static const unsigned int vin4_field_pins[] = {
1589 RCAR_GP_PIN(8, 16),
1590};
1591static const unsigned int vin4_field_mux[] = {
1592 VI4_FIELD_MARK,
1593};
1594static const unsigned int vin4_clkenb_pins[] = {
1595 RCAR_GP_PIN(8, 1),
1596};
1597static const unsigned int vin4_clkenb_mux[] = {
1598 VI4_CLKENB_MARK,
1599};
1600static const unsigned int vin4_clk_pins[] = {
1601 RCAR_GP_PIN(8, 0),
1602};
1603static const unsigned int vin4_clk_mux[] = {
1604 VI4_CLK_MARK,
1605};
1606/* - VIN5 ------------------------------------------------------------------- */
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1607static const unsigned int vin5_data_pins[] = {
1608 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1609 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1610 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1611 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1612 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1613 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1614};
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1615static const unsigned int vin5_data_mux[] = {
1616 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1617 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1618 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1619 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1620 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1621 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1622};
1623static const unsigned int vin5_sync_pins[] = {
1624 /* HSYNC#, VSYNC# */
1625 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1626};
1627static const unsigned int vin5_sync_mux[] = {
1628 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1629};
1630static const unsigned int vin5_field_pins[] = {
1631 RCAR_GP_PIN(9, 16),
1632};
1633static const unsigned int vin5_field_mux[] = {
1634 VI5_FIELD_MARK,
1635};
1636static const unsigned int vin5_clkenb_pins[] = {
1637 RCAR_GP_PIN(9, 1),
1638};
1639static const unsigned int vin5_clkenb_mux[] = {
1640 VI5_CLKENB_MARK,
1641};
1642static const unsigned int vin5_clk_pins[] = {
1643 RCAR_GP_PIN(9, 0),
1644};
1645static const unsigned int vin5_clk_mux[] = {
1646 VI5_CLK_MARK,
1647};
1648
1649static const struct sh_pfc_pin_group pinmux_groups[] = {
1650 SH_PFC_PIN_GROUP(avb_link),
1651 SH_PFC_PIN_GROUP(avb_magic),
1652 SH_PFC_PIN_GROUP(avb_phy_int),
1653 SH_PFC_PIN_GROUP(avb_mdio),
1654 SH_PFC_PIN_GROUP(avb_mii),
1655 SH_PFC_PIN_GROUP(avb_gmii),
1656 SH_PFC_PIN_GROUP(avb_avtp_match),
1657 SH_PFC_PIN_GROUP(can0_data),
1658 SH_PFC_PIN_GROUP(can1_data),
1659 SH_PFC_PIN_GROUP(can_clk),
1660 SH_PFC_PIN_GROUP(du0_rgb666),
1661 SH_PFC_PIN_GROUP(du0_rgb888),
1662 SH_PFC_PIN_GROUP(du0_sync),
1663 SH_PFC_PIN_GROUP(du0_oddf),
1664 SH_PFC_PIN_GROUP(du0_disp),
1665 SH_PFC_PIN_GROUP(du0_cde),
1666 SH_PFC_PIN_GROUP(du1_rgb666),
1667 SH_PFC_PIN_GROUP(du1_sync),
1668 SH_PFC_PIN_GROUP(du1_oddf),
1669 SH_PFC_PIN_GROUP(du1_disp),
1670 SH_PFC_PIN_GROUP(du1_cde),
1671 SH_PFC_PIN_GROUP(intc_irq0),
1672 SH_PFC_PIN_GROUP(intc_irq1),
1673 SH_PFC_PIN_GROUP(intc_irq2),
1674 SH_PFC_PIN_GROUP(intc_irq3),
1675 SH_PFC_PIN_GROUP(lbsc_cs0),
1676 SH_PFC_PIN_GROUP(lbsc_cs1),
1677 SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1678 SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1679 SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1680 SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1681 SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1682 SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1683 SH_PFC_PIN_GROUP(msiof0_clk),
1684 SH_PFC_PIN_GROUP(msiof0_sync),
1685 SH_PFC_PIN_GROUP(msiof0_rx),
1686 SH_PFC_PIN_GROUP(msiof0_tx),
1687 SH_PFC_PIN_GROUP(msiof1_clk),
1688 SH_PFC_PIN_GROUP(msiof1_sync),
1689 SH_PFC_PIN_GROUP(msiof1_rx),
1690 SH_PFC_PIN_GROUP(msiof1_tx),
1691 SH_PFC_PIN_GROUP(qspi_ctrl),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1692 BUS_DATA_PIN_GROUP(qspi_data, 2),
1693 BUS_DATA_PIN_GROUP(qspi_data, 4),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1694 SH_PFC_PIN_GROUP(scif0_data),
1695 SH_PFC_PIN_GROUP(scif0_clk),
1696 SH_PFC_PIN_GROUP(scif0_ctrl),
1697 SH_PFC_PIN_GROUP(scif1_data),
1698 SH_PFC_PIN_GROUP(scif1_clk),
1699 SH_PFC_PIN_GROUP(scif1_ctrl),
1700 SH_PFC_PIN_GROUP(scif2_data),
1701 SH_PFC_PIN_GROUP(scif2_clk),
1702 SH_PFC_PIN_GROUP(scif3_data),
1703 SH_PFC_PIN_GROUP(scif3_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1704 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
1705 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1706 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1707 SH_PFC_PIN_GROUP(sdhi0_cd),
1708 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1709 BUS_DATA_PIN_GROUP(vin0_data, 24),
1710 BUS_DATA_PIN_GROUP(vin0_data, 20),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1711 SH_PFC_PIN_GROUP(vin0_data18),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1712 BUS_DATA_PIN_GROUP(vin0_data, 16),
1713 BUS_DATA_PIN_GROUP(vin0_data, 12),
1714 BUS_DATA_PIN_GROUP(vin0_data, 10),
1715 BUS_DATA_PIN_GROUP(vin0_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1716 SH_PFC_PIN_GROUP(vin0_sync),
1717 SH_PFC_PIN_GROUP(vin0_field),
1718 SH_PFC_PIN_GROUP(vin0_clkenb),
1719 SH_PFC_PIN_GROUP(vin0_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1720 BUS_DATA_PIN_GROUP(vin1_data, 24),
1721 BUS_DATA_PIN_GROUP(vin1_data, 20),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1722 SH_PFC_PIN_GROUP(vin1_data18),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1723 BUS_DATA_PIN_GROUP(vin1_data, 16),
1724 BUS_DATA_PIN_GROUP(vin1_data, 12),
1725 BUS_DATA_PIN_GROUP(vin1_data, 10),
1726 BUS_DATA_PIN_GROUP(vin1_data, 8),
1727 BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
1728 BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1729 SH_PFC_PIN_GROUP(vin1_data18_b),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1730 BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1731 SH_PFC_PIN_GROUP(vin1_sync),
1732 SH_PFC_PIN_GROUP(vin1_field),
1733 SH_PFC_PIN_GROUP(vin1_clkenb),
1734 SH_PFC_PIN_GROUP(vin1_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1735 BUS_DATA_PIN_GROUP(vin2_data, 16),
1736 BUS_DATA_PIN_GROUP(vin2_data, 12),
1737 BUS_DATA_PIN_GROUP(vin2_data, 10),
1738 BUS_DATA_PIN_GROUP(vin2_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1739 SH_PFC_PIN_GROUP(vin2_sync),
1740 SH_PFC_PIN_GROUP(vin2_field),
1741 SH_PFC_PIN_GROUP(vin2_clkenb),
1742 SH_PFC_PIN_GROUP(vin2_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1743 BUS_DATA_PIN_GROUP(vin3_data, 16),
1744 BUS_DATA_PIN_GROUP(vin3_data, 12),
1745 BUS_DATA_PIN_GROUP(vin3_data, 10),
1746 BUS_DATA_PIN_GROUP(vin3_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1747 SH_PFC_PIN_GROUP(vin3_sync),
1748 SH_PFC_PIN_GROUP(vin3_field),
1749 SH_PFC_PIN_GROUP(vin3_clkenb),
1750 SH_PFC_PIN_GROUP(vin3_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1751 BUS_DATA_PIN_GROUP(vin4_data, 12),
1752 BUS_DATA_PIN_GROUP(vin4_data, 10),
1753 BUS_DATA_PIN_GROUP(vin4_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1754 SH_PFC_PIN_GROUP(vin4_sync),
1755 SH_PFC_PIN_GROUP(vin4_field),
1756 SH_PFC_PIN_GROUP(vin4_clkenb),
1757 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]1758 BUS_DATA_PIN_GROUP(vin5_data, 12),
1759 BUS_DATA_PIN_GROUP(vin5_data, 10),
1760 BUS_DATA_PIN_GROUP(vin5_data, 8),
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1761 SH_PFC_PIN_GROUP(vin5_sync),
1762 SH_PFC_PIN_GROUP(vin5_field),
1763 SH_PFC_PIN_GROUP(vin5_clkenb),
1764 SH_PFC_PIN_GROUP(vin5_clk),
1765};
1766
1767static const char * const avb_groups[] = {
1768 "avb_link",
1769 "avb_magic",
1770 "avb_phy_int",
1771 "avb_mdio",
1772 "avb_mii",
1773 "avb_gmii",
1774 "avb_avtp_match",
1775};
1776
1777static const char * const can0_groups[] = {
1778 "can0_data",
1779 "can_clk",
1780};
1781
1782static const char * const can1_groups[] = {
1783 "can1_data",
1784 "can_clk",
1785};
1786
1787static const char * const du0_groups[] = {
1788 "du0_rgb666",
1789 "du0_rgb888",
1790 "du0_sync",
1791 "du0_oddf",
1792 "du0_disp",
1793 "du0_cde",
1794};
1795
1796static const char * const du1_groups[] = {
1797 "du1_rgb666",
1798 "du1_sync",
1799 "du1_oddf",
1800 "du1_disp",
1801 "du1_cde",
1802};
1803
1804static const char * const intc_groups[] = {
1805 "intc_irq0",
1806 "intc_irq1",
1807 "intc_irq2",
1808 "intc_irq3",
1809};
1810
1811static const char * const lbsc_groups[] = {
1812 "lbsc_cs0",
1813 "lbsc_cs1",
1814 "lbsc_ex_cs0",
1815 "lbsc_ex_cs1",
1816 "lbsc_ex_cs2",
1817 "lbsc_ex_cs3",
1818 "lbsc_ex_cs4",
1819 "lbsc_ex_cs5",
1820};
1821
1822static const char * const msiof0_groups[] = {
1823 "msiof0_clk",
1824 "msiof0_sync",
1825 "msiof0_rx",
1826 "msiof0_tx",
1827};
1828
1829static const char * const msiof1_groups[] = {
1830 "msiof1_clk",
1831 "msiof1_sync",
1832 "msiof1_rx",
1833 "msiof1_tx",
1834};
1835
1836static const char * const qspi_groups[] = {
1837 "qspi_ctrl",
1838 "qspi_data2",
1839 "qspi_data4",
1840};
1841
1842static const char * const scif0_groups[] = {
1843 "scif0_data",
1844 "scif0_clk",
1845 "scif0_ctrl",
1846};
1847
1848static const char * const scif1_groups[] = {
1849 "scif1_data",
1850 "scif1_clk",
1851 "scif1_ctrl",
1852};
1853
1854static const char * const scif2_groups[] = {
1855 "scif2_data",
1856 "scif2_clk",
1857};
1858
1859static const char * const scif3_groups[] = {
1860 "scif3_data",
1861 "scif3_clk",
1862};
1863
1864static const char * const sdhi0_groups[] = {
1865 "sdhi0_data1",
1866 "sdhi0_data4",
1867 "sdhi0_ctrl",
1868 "sdhi0_cd",
1869 "sdhi0_wp",
1870};
1871
1872static const char * const vin0_groups[] = {
1873 "vin0_data24",
1874 "vin0_data20",
1875 "vin0_data18",
1876 "vin0_data16",
1877 "vin0_data12",
1878 "vin0_data10",
1879 "vin0_data8",
1880 "vin0_sync",
1881 "vin0_field",
1882 "vin0_clkenb",
1883 "vin0_clk",
1884};
1885
1886static const char * const vin1_groups[] = {
1887 "vin1_data24",
1888 "vin1_data20",
1889 "vin1_data18",
1890 "vin1_data16",
1891 "vin1_data12",
1892 "vin1_data10",
1893 "vin1_data8",
1894 "vin1_data24_b",
1895 "vin1_data20_b",
Marek Vasut0913c7a2019-03-04 22:26:28 +0100[diff] [blame]1896 "vin1_data18_b",
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1897 "vin1_data16_b",
1898 "vin1_sync",
1899 "vin1_field",
1900 "vin1_clkenb",
1901 "vin1_clk",
1902};
1903
1904static const char * const vin2_groups[] = {
1905 "vin2_data16",
1906 "vin2_data12",
1907 "vin2_data10",
1908 "vin2_data8",
1909 "vin2_sync",
1910 "vin2_field",
1911 "vin2_clkenb",
1912 "vin2_clk",
1913};
1914
1915static const char * const vin3_groups[] = {
1916 "vin3_data16",
1917 "vin3_data12",
1918 "vin3_data10",
1919 "vin3_data8",
1920 "vin3_sync",
1921 "vin3_field",
1922 "vin3_clkenb",
1923 "vin3_clk",
1924};
1925
1926static const char * const vin4_groups[] = {
1927 "vin4_data12",
1928 "vin4_data10",
1929 "vin4_data8",
1930 "vin4_sync",
1931 "vin4_field",
1932 "vin4_clkenb",
1933 "vin4_clk",
1934};
1935
1936static const char * const vin5_groups[] = {
1937 "vin5_data12",
1938 "vin5_data10",
1939 "vin5_data8",
1940 "vin5_sync",
1941 "vin5_field",
1942 "vin5_clkenb",
1943 "vin5_clk",
1944};
1945
1946static const struct sh_pfc_function pinmux_functions[] = {
1947 SH_PFC_FUNCTION(avb),
1948 SH_PFC_FUNCTION(can0),
1949 SH_PFC_FUNCTION(can1),
1950 SH_PFC_FUNCTION(du0),
1951 SH_PFC_FUNCTION(du1),
1952 SH_PFC_FUNCTION(intc),
1953 SH_PFC_FUNCTION(lbsc),
1954 SH_PFC_FUNCTION(msiof0),
1955 SH_PFC_FUNCTION(msiof1),
1956 SH_PFC_FUNCTION(qspi),
1957 SH_PFC_FUNCTION(scif0),
1958 SH_PFC_FUNCTION(scif1),
1959 SH_PFC_FUNCTION(scif2),
1960 SH_PFC_FUNCTION(scif3),
1961 SH_PFC_FUNCTION(sdhi0),
1962 SH_PFC_FUNCTION(vin0),
1963 SH_PFC_FUNCTION(vin1),
1964 SH_PFC_FUNCTION(vin2),
1965 SH_PFC_FUNCTION(vin3),
1966 SH_PFC_FUNCTION(vin4),
1967 SH_PFC_FUNCTION(vin5),
1968};
1969
1970static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1971 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]1972 0, 0,
1973 0, 0,
1974 0, 0,
1975 GP_0_28_FN, FN_IP1_4,
1976 GP_0_27_FN, FN_IP1_3,
1977 GP_0_26_FN, FN_IP1_2,
1978 GP_0_25_FN, FN_IP1_1,
1979 GP_0_24_FN, FN_IP1_0,
1980 GP_0_23_FN, FN_IP0_23,
1981 GP_0_22_FN, FN_IP0_22,
1982 GP_0_21_FN, FN_IP0_21,
1983 GP_0_20_FN, FN_IP0_20,
1984 GP_0_19_FN, FN_IP0_19,
1985 GP_0_18_FN, FN_IP0_18,
1986 GP_0_17_FN, FN_IP0_17,
1987 GP_0_16_FN, FN_IP0_16,
1988 GP_0_15_FN, FN_IP0_15,
1989 GP_0_14_FN, FN_IP0_14,
1990 GP_0_13_FN, FN_IP0_13,
1991 GP_0_12_FN, FN_IP0_12,
1992 GP_0_11_FN, FN_IP0_11,
1993 GP_0_10_FN, FN_IP0_10,
1994 GP_0_9_FN, FN_IP0_9,
1995 GP_0_8_FN, FN_IP0_8,
1996 GP_0_7_FN, FN_IP0_7,
1997 GP_0_6_FN, FN_IP0_6,
1998 GP_0_5_FN, FN_IP0_5,
1999 GP_0_4_FN, FN_IP0_4,
2000 GP_0_3_FN, FN_IP0_3,
2001 GP_0_2_FN, FN_IP0_2,
2002 GP_0_1_FN, FN_IP0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2003 GP_0_0_FN, FN_IP0_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2004 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2005 { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
2006 GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2007 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2008 GROUP(
2009 /* GP1_31_23 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2010 GP_1_22_FN, FN_DU1_CDE,
2011 GP_1_21_FN, FN_DU1_DISP,
2012 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2013 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
2014 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
2015 GP_1_17_FN, FN_DU1_DB7_C5,
2016 GP_1_16_FN, FN_DU1_DB6_C4,
2017 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
2018 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
2019 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
2020 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
2021 GP_1_11_FN, FN_IP1_16,
2022 GP_1_10_FN, FN_IP1_15,
2023 GP_1_9_FN, FN_IP1_14,
2024 GP_1_8_FN, FN_IP1_13,
2025 GP_1_7_FN, FN_IP1_12,
2026 GP_1_6_FN, FN_IP1_11,
2027 GP_1_5_FN, FN_IP1_10,
2028 GP_1_4_FN, FN_IP1_9,
2029 GP_1_3_FN, FN_IP1_8,
2030 GP_1_2_FN, FN_IP1_7,
2031 GP_1_1_FN, FN_IP1_6,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2032 GP_1_0_FN, FN_IP1_5, ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2033 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2034 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2035 GP_2_31_FN, FN_A15,
2036 GP_2_30_FN, FN_A14,
2037 GP_2_29_FN, FN_A13,
2038 GP_2_28_FN, FN_A12,
2039 GP_2_27_FN, FN_A11,
2040 GP_2_26_FN, FN_A10,
2041 GP_2_25_FN, FN_A9,
2042 GP_2_24_FN, FN_A8,
2043 GP_2_23_FN, FN_A7,
2044 GP_2_22_FN, FN_A6,
2045 GP_2_21_FN, FN_A5,
2046 GP_2_20_FN, FN_A4,
2047 GP_2_19_FN, FN_A3,
2048 GP_2_18_FN, FN_A2,
2049 GP_2_17_FN, FN_A1,
2050 GP_2_16_FN, FN_A0,
2051 GP_2_15_FN, FN_D15,
2052 GP_2_14_FN, FN_D14,
2053 GP_2_13_FN, FN_D13,
2054 GP_2_12_FN, FN_D12,
2055 GP_2_11_FN, FN_D11,
2056 GP_2_10_FN, FN_D10,
2057 GP_2_9_FN, FN_D9,
2058 GP_2_8_FN, FN_D8,
2059 GP_2_7_FN, FN_D7,
2060 GP_2_6_FN, FN_D6,
2061 GP_2_5_FN, FN_D5,
2062 GP_2_4_FN, FN_D4,
2063 GP_2_3_FN, FN_D3,
2064 GP_2_2_FN, FN_D2,
2065 GP_2_1_FN, FN_D1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2066 GP_2_0_FN, FN_D0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2067 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2068 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2069 0, 0,
2070 0, 0,
2071 0, 0,
2072 0, 0,
2073 GP_3_27_FN, FN_CS0_N,
2074 GP_3_26_FN, FN_IP1_22,
2075 GP_3_25_FN, FN_IP1_21,
2076 GP_3_24_FN, FN_IP1_20,
2077 GP_3_23_FN, FN_IP1_19,
2078 GP_3_22_FN, FN_IRQ3,
2079 GP_3_21_FN, FN_IRQ2,
2080 GP_3_20_FN, FN_IRQ1,
2081 GP_3_19_FN, FN_IRQ0,
2082 GP_3_18_FN, FN_EX_WAIT0,
2083 GP_3_17_FN, FN_WE1_N,
2084 GP_3_16_FN, FN_WE0_N,
2085 GP_3_15_FN, FN_RD_WR_N,
2086 GP_3_14_FN, FN_RD_N,
2087 GP_3_13_FN, FN_BS_N,
2088 GP_3_12_FN, FN_EX_CS5_N,
2089 GP_3_11_FN, FN_EX_CS4_N,
2090 GP_3_10_FN, FN_EX_CS3_N,
2091 GP_3_9_FN, FN_EX_CS2_N,
2092 GP_3_8_FN, FN_EX_CS1_N,
2093 GP_3_7_FN, FN_EX_CS0_N,
2094 GP_3_6_FN, FN_CS1_N_A26,
2095 GP_3_5_FN, FN_IP1_18,
2096 GP_3_4_FN, FN_IP1_17,
2097 GP_3_3_FN, FN_A19,
2098 GP_3_2_FN, FN_A18,
2099 GP_3_1_FN, FN_A17,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2100 GP_3_0_FN, FN_A16 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2101 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2102 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32,
2103 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2104 1, 1, 1, 1, 1, 1),
2105 GROUP(
2106 /* GP4_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2107 GP_4_16_FN, FN_VI0_FIELD,
2108 GP_4_15_FN, FN_VI0_D11_G3_Y3,
2109 GP_4_14_FN, FN_VI0_D10_G2_Y2,
2110 GP_4_13_FN, FN_VI0_D9_G1_Y1,
2111 GP_4_12_FN, FN_VI0_D8_G0_Y0,
2112 GP_4_11_FN, FN_VI0_D7_B7_C7,
2113 GP_4_10_FN, FN_VI0_D6_B6_C6,
2114 GP_4_9_FN, FN_VI0_D5_B5_C5,
2115 GP_4_8_FN, FN_VI0_D4_B4_C4,
2116 GP_4_7_FN, FN_VI0_D3_B3_C3,
2117 GP_4_6_FN, FN_VI0_D2_B2_C2,
2118 GP_4_5_FN, FN_VI0_D1_B1_C1,
2119 GP_4_4_FN, FN_VI0_D0_B0_C0,
2120 GP_4_3_FN, FN_VI0_VSYNC_N,
2121 GP_4_2_FN, FN_VI0_HSYNC_N,
2122 GP_4_1_FN, FN_VI0_CLKENB,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2123 GP_4_0_FN, FN_VI0_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2124 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2125 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32,
2126 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2127 1, 1, 1, 1, 1, 1),
2128 GROUP(
2129 /* GP5_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2130 GP_5_16_FN, FN_VI1_FIELD,
2131 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2132 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2133 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2134 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2135 GP_5_11_FN, FN_VI1_D7_B7_C7,
2136 GP_5_10_FN, FN_VI1_D6_B6_C6,
2137 GP_5_9_FN, FN_VI1_D5_B5_C5,
2138 GP_5_8_FN, FN_VI1_D4_B4_C4,
2139 GP_5_7_FN, FN_VI1_D3_B3_C3,
2140 GP_5_6_FN, FN_VI1_D2_B2_C2,
2141 GP_5_5_FN, FN_VI1_D1_B1_C1,
2142 GP_5_4_FN, FN_VI1_D0_B0_C0,
2143 GP_5_3_FN, FN_VI1_VSYNC_N,
2144 GP_5_2_FN, FN_VI1_HSYNC_N,
2145 GP_5_1_FN, FN_VI1_CLKENB,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2146 GP_5_0_FN, FN_VI1_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2147 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2148 { PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32,
2149 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2150 1, 1, 1, 1, 1, 1),
2151 GROUP(
2152 /* GP6_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2153 GP_6_16_FN, FN_IP2_16,
2154 GP_6_15_FN, FN_IP2_15,
2155 GP_6_14_FN, FN_IP2_14,
2156 GP_6_13_FN, FN_IP2_13,
2157 GP_6_12_FN, FN_IP2_12,
2158 GP_6_11_FN, FN_IP2_11,
2159 GP_6_10_FN, FN_IP2_10,
2160 GP_6_9_FN, FN_IP2_9,
2161 GP_6_8_FN, FN_IP2_8,
2162 GP_6_7_FN, FN_IP2_7,
2163 GP_6_6_FN, FN_IP2_6,
2164 GP_6_5_FN, FN_IP2_5,
2165 GP_6_4_FN, FN_IP2_4,
2166 GP_6_3_FN, FN_IP2_3,
2167 GP_6_2_FN, FN_IP2_2,
2168 GP_6_1_FN, FN_IP2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2169 GP_6_0_FN, FN_IP2_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2170 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2171 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32,
2172 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2173 1, 1, 1, 1, 1, 1),
2174 GROUP(
2175 /* GP7_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2176 GP_7_16_FN, FN_VI3_FIELD,
2177 GP_7_15_FN, FN_IP3_14,
2178 GP_7_14_FN, FN_VI3_D10_Y2,
2179 GP_7_13_FN, FN_IP3_13,
2180 GP_7_12_FN, FN_IP3_12,
2181 GP_7_11_FN, FN_IP3_11,
2182 GP_7_10_FN, FN_IP3_10,
2183 GP_7_9_FN, FN_IP3_9,
2184 GP_7_8_FN, FN_IP3_8,
2185 GP_7_7_FN, FN_IP3_7,
2186 GP_7_6_FN, FN_IP3_6,
2187 GP_7_5_FN, FN_IP3_5,
2188 GP_7_4_FN, FN_IP3_4,
2189 GP_7_3_FN, FN_IP3_3,
2190 GP_7_2_FN, FN_IP3_2,
2191 GP_7_1_FN, FN_IP3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2192 GP_7_0_FN, FN_IP3_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2193 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2194 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32,
2195 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2196 1, 1, 1, 1, 1, 1),
2197 GROUP(
2198 /* GP8_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2199 GP_8_16_FN, FN_IP4_24,
2200 GP_8_15_FN, FN_IP4_23,
2201 GP_8_14_FN, FN_IP4_22,
2202 GP_8_13_FN, FN_IP4_21,
2203 GP_8_12_FN, FN_IP4_20_19,
2204 GP_8_11_FN, FN_IP4_18_17,
2205 GP_8_10_FN, FN_IP4_16_15,
2206 GP_8_9_FN, FN_IP4_14_13,
2207 GP_8_8_FN, FN_IP4_12_11,
2208 GP_8_7_FN, FN_IP4_10_9,
2209 GP_8_6_FN, FN_IP4_8_7,
2210 GP_8_5_FN, FN_IP4_6_5,
2211 GP_8_4_FN, FN_IP4_4,
2212 GP_8_3_FN, FN_IP4_3_2,
2213 GP_8_2_FN, FN_IP4_1,
2214 GP_8_1_FN, FN_IP4_0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2215 GP_8_0_FN, FN_VI4_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2216 },
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2217 { PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32,
2218 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2219 1, 1, 1, 1, 1, 1),
2220 GROUP(
2221 /* GP9_31_17 RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2222 GP_9_16_FN, FN_VI5_FIELD,
2223 GP_9_15_FN, FN_VI5_D11_Y3,
2224 GP_9_14_FN, FN_VI5_D10_Y2,
2225 GP_9_13_FN, FN_VI5_D9_Y1,
2226 GP_9_12_FN, FN_IP5_11,
2227 GP_9_11_FN, FN_IP5_10,
2228 GP_9_10_FN, FN_IP5_9,
2229 GP_9_9_FN, FN_IP5_8,
2230 GP_9_8_FN, FN_IP5_7,
2231 GP_9_7_FN, FN_IP5_6,
2232 GP_9_6_FN, FN_IP5_5,
2233 GP_9_5_FN, FN_IP5_4,
2234 GP_9_4_FN, FN_IP5_3,
2235 GP_9_3_FN, FN_IP5_2,
2236 GP_9_2_FN, FN_IP5_1,
2237 GP_9_1_FN, FN_IP5_0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2238 GP_9_0_FN, FN_VI5_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2239 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2240 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2241 GP_10_31_FN, FN_CAN1_RX,
2242 GP_10_30_FN, FN_CAN1_TX,
2243 GP_10_29_FN, FN_CAN_CLK,
2244 GP_10_28_FN, FN_CAN0_RX,
2245 GP_10_27_FN, FN_CAN0_TX,
2246 GP_10_26_FN, FN_SCIF_CLK,
2247 GP_10_25_FN, FN_IP6_18_17,
2248 GP_10_24_FN, FN_IP6_16,
2249 GP_10_23_FN, FN_IP6_15_14,
2250 GP_10_22_FN, FN_IP6_13_12,
2251 GP_10_21_FN, FN_IP6_11_10,
2252 GP_10_20_FN, FN_IP6_9_8,
2253 GP_10_19_FN, FN_RX1,
2254 GP_10_18_FN, FN_TX1,
2255 GP_10_17_FN, FN_RTS1_N,
2256 GP_10_16_FN, FN_CTS1_N,
2257 GP_10_15_FN, FN_SCK1,
2258 GP_10_14_FN, FN_RX0,
2259 GP_10_13_FN, FN_TX0,
2260 GP_10_12_FN, FN_RTS0_N,
2261 GP_10_11_FN, FN_CTS0_N,
2262 GP_10_10_FN, FN_SCK0,
2263 GP_10_9_FN, FN_IP6_7,
2264 GP_10_8_FN, FN_IP6_6,
2265 GP_10_7_FN, FN_HCTS1_N,
2266 GP_10_6_FN, FN_IP6_5,
2267 GP_10_5_FN, FN_IP6_4,
2268 GP_10_4_FN, FN_IP6_3,
2269 GP_10_3_FN, FN_IP6_2,
2270 GP_10_2_FN, FN_HRTS0_N,
2271 GP_10_1_FN, FN_IP6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2272 GP_10_0_FN, FN_IP6_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2273 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2274 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2275 0, 0,
2276 0, 0,
2277 GP_11_29_FN, FN_AVS2,
2278 GP_11_28_FN, FN_AVS1,
2279 GP_11_27_FN, FN_ADICHS2,
2280 GP_11_26_FN, FN_ADICHS1,
2281 GP_11_25_FN, FN_ADICHS0,
2282 GP_11_24_FN, FN_ADIDATA,
2283 GP_11_23_FN, FN_ADICS_SAMP,
2284 GP_11_22_FN, FN_ADICLK,
2285 GP_11_21_FN, FN_IP7_20,
2286 GP_11_20_FN, FN_IP7_19,
2287 GP_11_19_FN, FN_IP7_18,
2288 GP_11_18_FN, FN_IP7_17,
2289 GP_11_17_FN, FN_IP7_16,
2290 GP_11_16_FN, FN_IP7_15_14,
2291 GP_11_15_FN, FN_IP7_13_12,
2292 GP_11_14_FN, FN_IP7_11_10,
2293 GP_11_13_FN, FN_IP7_9_8,
2294 GP_11_12_FN, FN_SD0_WP,
2295 GP_11_11_FN, FN_SD0_CD,
2296 GP_11_10_FN, FN_SD0_DAT3,
2297 GP_11_9_FN, FN_SD0_DAT2,
2298 GP_11_8_FN, FN_SD0_DAT1,
2299 GP_11_7_FN, FN_SD0_DAT0,
2300 GP_11_6_FN, FN_SD0_CMD,
2301 GP_11_5_FN, FN_SD0_CLK,
2302 GP_11_4_FN, FN_IP7_7,
2303 GP_11_3_FN, FN_IP7_6,
2304 GP_11_2_FN, FN_IP7_5_4,
2305 GP_11_1_FN, FN_IP7_3_2,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2306 GP_11_0_FN, FN_IP7_1_0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2307 },
2308 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2309 GROUP(-8,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2310 1, 1, 1, 1, 1, 1, 1, 1,
2311 1, 1, 1, 1, 1, 1, 1, 1,
2312 1, 1, 1, 1, 1, 1, 1, 1),
2313 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2314 /* IP0_31_24 [8] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2315 /* IP0_23 [1] */
2316 FN_DU0_DB7_C5, 0,
2317 /* IP0_22 [1] */
2318 FN_DU0_DB6_C4, 0,
2319 /* IP0_21 [1] */
2320 FN_DU0_DB5_C3, 0,
2321 /* IP0_20 [1] */
2322 FN_DU0_DB4_C2, 0,
2323 /* IP0_19 [1] */
2324 FN_DU0_DB3_C1, 0,
2325 /* IP0_18 [1] */
2326 FN_DU0_DB2_C0, 0,
2327 /* IP0_17 [1] */
2328 FN_DU0_DB1, 0,
2329 /* IP0_16 [1] */
2330 FN_DU0_DB0, 0,
2331 /* IP0_15 [1] */
2332 FN_DU0_DG7_Y3_DATA15, 0,
2333 /* IP0_14 [1] */
2334 FN_DU0_DG6_Y2_DATA14, 0,
2335 /* IP0_13 [1] */
2336 FN_DU0_DG5_Y1_DATA13, 0,
2337 /* IP0_12 [1] */
2338 FN_DU0_DG4_Y0_DATA12, 0,
2339 /* IP0_11 [1] */
2340 FN_DU0_DG3_C7_DATA11, 0,
2341 /* IP0_10 [1] */
2342 FN_DU0_DG2_C6_DATA10, 0,
2343 /* IP0_9 [1] */
2344 FN_DU0_DG1_DATA9, 0,
2345 /* IP0_8 [1] */
2346 FN_DU0_DG0_DATA8, 0,
2347 /* IP0_7 [1] */
2348 FN_DU0_DR7_Y9_DATA7, 0,
2349 /* IP0_6 [1] */
2350 FN_DU0_DR6_Y8_DATA6, 0,
2351 /* IP0_5 [1] */
2352 FN_DU0_DR5_Y7_DATA5, 0,
2353 /* IP0_4 [1] */
2354 FN_DU0_DR4_Y6_DATA4, 0,
2355 /* IP0_3 [1] */
2356 FN_DU0_DR3_Y5_DATA3, 0,
2357 /* IP0_2 [1] */
2358 FN_DU0_DR2_Y4_DATA2, 0,
2359 /* IP0_1 [1] */
2360 FN_DU0_DR1_DATA1, 0,
2361 /* IP0_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2362 FN_DU0_DR0_DATA0, 0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2363 },
2364 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2365 GROUP(-9, 1, 1, 1, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2366 1, 1, 1, 1, 1, 1, 1, 1,
2367 1, 1, 1, 1, 1, 1, 1, 1),
2368 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2369 /* IP1_31_23 [9] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2370 /* IP1_22 [1] */
2371 FN_A25, FN_SSL,
2372 /* IP1_21 [1] */
2373 FN_A24, FN_SPCLK,
2374 /* IP1_20 [1] */
2375 FN_A23, FN_IO3,
2376 /* IP1_19 [1] */
2377 FN_A22, FN_IO2,
2378 /* IP1_18 [1] */
2379 FN_A21, FN_MISO_IO1,
2380 /* IP1_17 [1] */
2381 FN_A20, FN_MOSI_IO0,
2382 /* IP1_16 [1] */
2383 FN_DU1_DG7_Y3_DATA11, 0,
2384 /* IP1_15 [1] */
2385 FN_DU1_DG6_Y2_DATA10, 0,
2386 /* IP1_14 [1] */
2387 FN_DU1_DG5_Y1_DATA9, 0,
2388 /* IP1_13 [1] */
2389 FN_DU1_DG4_Y0_DATA8, 0,
2390 /* IP1_12 [1] */
2391 FN_DU1_DG3_C7_DATA7, 0,
2392 /* IP1_11 [1] */
2393 FN_DU1_DG2_C6_DATA6, 0,
2394 /* IP1_10 [1] */
2395 FN_DU1_DR7_DATA5, 0,
2396 /* IP1_9 [1] */
2397 FN_DU1_DR6_DATA4, 0,
2398 /* IP1_8 [1] */
2399 FN_DU1_DR5_Y7_DATA3, 0,
2400 /* IP1_7 [1] */
2401 FN_DU1_DR4_Y6_DATA2, 0,
2402 /* IP1_6 [1] */
2403 FN_DU1_DR3_Y5_DATA1, 0,
2404 /* IP1_5 [1] */
2405 FN_DU1_DR2_Y4_DATA0, 0,
2406 /* IP1_4 [1] */
2407 FN_DU0_CDE, 0,
2408 /* IP1_3 [1] */
2409 FN_DU0_DISP, 0,
2410 /* IP1_2 [1] */
2411 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2412 /* IP1_1 [1] */
2413 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2414 /* IP1_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2415 FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2416 },
2417 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2418 GROUP(-15, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2419 1, 1, 1, 1, 1, 1, 1, 1,
2420 1, 1, 1, 1, 1, 1, 1, 1),
2421 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2422 /* IP2_31_17 [15] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2423 /* IP2_16 [1] */
2424 FN_VI2_FIELD, FN_AVB_TXD2,
2425 /* IP2_15 [1] */
2426 FN_VI2_D11_Y3, FN_AVB_TXD1,
2427 /* IP2_14 [1] */
2428 FN_VI2_D10_Y2, FN_AVB_TXD0,
2429 /* IP2_13 [1] */
2430 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2431 /* IP2_12 [1] */
2432 FN_VI2_D8_Y0, FN_AVB_TXD3,
2433 /* IP2_11 [1] */
2434 FN_VI2_D7_C7, FN_AVB_COL,
2435 /* IP2_10 [1] */
2436 FN_VI2_D6_C6, FN_AVB_RX_ER,
2437 /* IP2_9 [1] */
2438 FN_VI2_D5_C5, FN_AVB_RXD7,
2439 /* IP2_8 [1] */
2440 FN_VI2_D4_C4, FN_AVB_RXD6,
2441 /* IP2_7 [1] */
2442 FN_VI2_D3_C3, FN_AVB_RXD5,
2443 /* IP2_6 [1] */
2444 FN_VI2_D2_C2, FN_AVB_RXD4,
2445 /* IP2_5 [1] */
2446 FN_VI2_D1_C1, FN_AVB_RXD3,
2447 /* IP2_4 [1] */
2448 FN_VI2_D0_C0, FN_AVB_RXD2,
2449 /* IP2_3 [1] */
2450 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2451 /* IP2_2 [1] */
2452 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2453 /* IP2_1 [1] */
2454 FN_VI2_CLKENB, FN_AVB_RX_DV,
2455 /* IP2_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2456 FN_VI2_CLK, FN_AVB_RX_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2457 },
2458 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2459 GROUP(-17, 1, 1, 1, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2460 1, 1, 1, 1, 1, 1, 1, 1),
2461 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2462 /* IP3_31_15 [17] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2463 /* IP3_14 [1] */
2464 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2465 /* IP3_13 [1] */
2466 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2467 /* IP3_12 [1] */
2468 FN_VI3_D8_Y0, FN_AVB_CRS,
2469 /* IP3_11 [1] */
2470 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2471 /* IP3_10 [1] */
2472 FN_VI3_D6_C6, FN_AVB_MAGIC,
2473 /* IP3_9 [1] */
2474 FN_VI3_D5_C5, FN_AVB_LINK,
2475 /* IP3_8 [1] */
2476 FN_VI3_D4_C4, FN_AVB_MDIO,
2477 /* IP3_7 [1] */
2478 FN_VI3_D3_C3, FN_AVB_MDC,
2479 /* IP3_6 [1] */
2480 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2481 /* IP3_5 [1] */
2482 FN_VI3_D1_C1, FN_AVB_TX_ER,
2483 /* IP3_4 [1] */
2484 FN_VI3_D0_C0, FN_AVB_TXD7,
2485 /* IP3_3 [1] */
2486 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2487 /* IP3_2 [1] */
2488 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2489 /* IP3_1 [1] */
2490 FN_VI3_CLKENB, FN_AVB_TXD4,
2491 /* IP3_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2492 FN_VI3_CLK, FN_AVB_TX_CLK ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2493 },
2494 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2495 GROUP(-7, 1, 1, 1, 1, 2, 2, 2,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2496 2, 2, 2, 2, 2, 1, 2, 1, 1),
2497 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2498 /* IP4_31_25 [7] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2499 /* IP4_24 [1] */
2500 FN_VI4_FIELD, FN_VI3_D15_Y7,
2501 /* IP4_23 [1] */
2502 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2503 /* IP4_22 [1] */
2504 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2505 /* IP4_21 [1] */
2506 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2507 /* IP4_20_19 [2] */
2508 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2509 /* IP4_18_17 [2] */
2510 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2511 /* IP4_16_15 [2] */
2512 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2513 /* IP4_14_13 [2] */
2514 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2515 /* IP4_12_11 [2] */
2516 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2517 /* IP4_10_9 [2] */
2518 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2519 /* IP4_8_7 [2] */
2520 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2521 /* IP4_6_5 [2] */
2522 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2523 /* IP4_4 [1] */
2524 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2525 /* IP4_3_2 [2] */
2526 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2527 /* IP4_1 [1] */
2528 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2529 /* IP4_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2530 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2531 },
2532 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2533 GROUP(-20, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2534 1, 1, 1, 1, 1, 1, 1, 1),
2535 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2536 /* IP5_31_12 [20] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2537 /* IP5_11 [1] */
2538 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2539 /* IP5_10 [1] */
2540 FN_VI5_D7_C7, FN_VI1_D22_R6,
2541 /* IP5_9 [1] */
2542 FN_VI5_D6_C6, FN_VI1_D21_R5,
2543 /* IP5_8 [1] */
2544 FN_VI5_D5_C5, FN_VI1_D20_R4,
2545 /* IP5_7 [1] */
2546 FN_VI5_D4_C4, FN_VI1_D19_R3,
2547 /* IP5_6 [1] */
2548 FN_VI5_D3_C3, FN_VI1_D18_R2,
2549 /* IP5_5 [1] */
2550 FN_VI5_D2_C2, FN_VI1_D17_R1,
2551 /* IP5_4 [1] */
2552 FN_VI5_D1_C1, FN_VI1_D16_R0,
2553 /* IP5_3 [1] */
2554 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2555 /* IP5_2 [1] */
2556 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2557 /* IP5_1 [1] */
2558 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2559 /* IP5_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2560 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2561 },
2562 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2563 GROUP(-13, 2, 1, 2, 2, 2, 2,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2564 1, 1, 1, 1, 1, 1, 1, 1),
2565 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2566 /* IP6_31_19 [13] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2567 /* IP6_18_17 [2] */
2568 FN_DREQ1_N, FN_RX3, 0, 0,
2569 /* IP6_16 [1] */
2570 FN_TX3, 0,
2571 /* IP6_15_14 [2] */
2572 FN_DACK1, FN_SCK3, 0, 0,
2573 /* IP6_13_12 [2] */
2574 FN_DREQ0_N, FN_RX2, 0, 0,
2575 /* IP6_11_10 [2] */
2576 FN_DACK0, FN_TX2, 0, 0,
2577 /* IP6_9_8 [2] */
2578 FN_DRACK0, FN_SCK2, 0, 0,
2579 /* IP6_7 [1] */
2580 FN_MSIOF1_RXD, FN_HRX1,
2581 /* IP6_6 [1] */
2582 FN_MSIOF1_TXD, FN_HTX1,
2583 /* IP6_5 [1] */
2584 FN_MSIOF1_SYNC, FN_HRTS1_N,
2585 /* IP6_4 [1] */
2586 FN_MSIOF1_SCK, FN_HSCK1,
2587 /* IP6_3 [1] */
2588 FN_MSIOF0_RXD, FN_HRX0,
2589 /* IP6_2 [1] */
2590 FN_MSIOF0_TXD, FN_HTX0,
2591 /* IP6_1 [1] */
2592 FN_MSIOF0_SYNC, FN_HCTS0_N,
2593 /* IP6_0 [1] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2594 FN_MSIOF0_SCK, FN_HSCK0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2595 },
2596 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2597 GROUP(-11, 1, 1, 1, 1, 1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2598 2, 2, 2, 2,
2599 1, 1, 2, 2, 2),
2600 GROUP(
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2601 /* IP7_31_21 [11] RESERVED */
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2602 /* IP7_20 [1] */
2603 FN_AUDIO_CLKB, 0,
2604 /* IP7_19 [1] */
2605 FN_AUDIO_CLKA, 0,
2606 /* IP7_18 [1] */
2607 FN_AUDIO_CLKOUT, 0,
2608 /* IP7_17 [1] */
2609 FN_SSI_SDATA4, 0,
2610 /* IP7_16 [1] */
2611 FN_SSI_WS4, 0,
2612 /* IP7_15_14 [2] */
2613 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2614 /* IP7_13_12 [2] */
2615 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2616 /* IP7_11_10 [2] */
2617 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2618 /* IP7_9_8 [2] */
2619 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2620 /* IP7_7 [1] */
2621 FN_PWM4, 0,
2622 /* IP7_6 [1] */
2623 FN_PWM3, 0,
2624 /* IP7_5_4 [2] */
2625 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2626 /* IP7_3_2 [2] */
2627 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2628 /* IP7_1_0 [2] */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2629 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2630 },
Marek Vasut78861462023-09-17 16:08:38 +0200[diff] [blame]2631 { /* sentinel */ }
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]2632};
2633
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]2634static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2635 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
2636 [ 0] = RCAR_GP_PIN(0, 0), /* DU0_DR0_DATA0 */
2637 [ 1] = RCAR_GP_PIN(0, 1), /* DU0_DR1_DATA1 */
2638 [ 2] = RCAR_GP_PIN(0, 2), /* DU0_DR2_Y4_DATA2 */
2639 [ 3] = RCAR_GP_PIN(0, 3), /* DU0_DR3_Y5_DATA3 */
2640 [ 4] = RCAR_GP_PIN(0, 4), /* DU0_DR4_Y6_DATA4 */
2641 [ 5] = RCAR_GP_PIN(0, 5), /* DU0_DR5_Y7_DATA5 */
2642 [ 6] = RCAR_GP_PIN(0, 6), /* DU0_DR6_Y8_DATA6 */
2643 [ 7] = RCAR_GP_PIN(0, 7), /* DU0_DR7_Y9_DATA7 */
2644 [ 8] = RCAR_GP_PIN(0, 8), /* DU0_DG0_DATA8 */
2645 [ 9] = RCAR_GP_PIN(0, 9), /* DU0_DG1_DATA9 */
2646 [10] = RCAR_GP_PIN(0, 10), /* DU0_DG2_C6_DATA10 */
2647 [11] = RCAR_GP_PIN(0, 11), /* DU0_DG3_C7_DATA11 */
2648 [12] = RCAR_GP_PIN(0, 12), /* DU0_DG4_Y0_DATA12 */
2649 [13] = RCAR_GP_PIN(0, 13), /* DU0_DG5_Y1_DATA13 */
2650 [14] = RCAR_GP_PIN(0, 14), /* DU0_DG6_Y2_DATA14 */
2651 [15] = RCAR_GP_PIN(0, 15), /* DU0_DG7_Y3_DATA15 */
2652 [16] = RCAR_GP_PIN(0, 16), /* DU0_DB0 */
2653 [17] = RCAR_GP_PIN(0, 17), /* DU0_DB1 */
2654 [18] = RCAR_GP_PIN(0, 18), /* DU0_DB2_C0 */
2655 [19] = RCAR_GP_PIN(0, 19), /* DU0_DB3_C1 */
2656 [20] = RCAR_GP_PIN(0, 20), /* DU0_DB4_C2 */
2657 [21] = RCAR_GP_PIN(0, 21), /* DU0_DB5_C3 */
2658 [22] = RCAR_GP_PIN(0, 22), /* DU0_DB6_C4 */
2659 [23] = RCAR_GP_PIN(0, 23), /* DU0_DB7_C5 */
2660 [24] = RCAR_GP_PIN(0, 24), /* DU0_EXHSYNC/DU0_HSYNC */
2661 [25] = RCAR_GP_PIN(0, 25), /* DU0_EXVSYNC/DU0_VSYNC */
2662 [26] = RCAR_GP_PIN(0, 26), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
2663 [27] = RCAR_GP_PIN(0, 27), /* DU0_DISP */
2664 [28] = RCAR_GP_PIN(0, 28), /* DU0_CDE */
2665 [29] = SH_PFC_PIN_NONE,
2666 [30] = SH_PFC_PIN_NONE,
2667 [31] = SH_PFC_PIN_NONE,
2668 } },
2669 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
2670 [ 0] = RCAR_GP_PIN(1, 0), /* DU1_DR2_Y4_DATA0 */
2671 [ 1] = RCAR_GP_PIN(1, 1), /* DU1_DR3_Y5_DATA1 */
2672 [ 2] = RCAR_GP_PIN(1, 2), /* DU1_DR4_Y6_DATA2 */
2673 [ 3] = RCAR_GP_PIN(1, 3), /* DU1_DR5_Y7_DATA3 */
2674 [ 4] = RCAR_GP_PIN(1, 4), /* DU1_DR6_DATA4 */
2675 [ 5] = RCAR_GP_PIN(1, 5), /* DU1_DR7_DATA5 */
2676 [ 6] = RCAR_GP_PIN(1, 6), /* DU1_DG2_C6_DATA6 */
2677 [ 7] = RCAR_GP_PIN(1, 7), /* DU1_DG3_C7_DATA7 */
2678 [ 8] = RCAR_GP_PIN(1, 8), /* DU1_DG4_Y0_DATA8 */
2679 [ 9] = RCAR_GP_PIN(1, 9), /* DU1_DG5_Y1_DATA9 */
2680 [10] = RCAR_GP_PIN(1, 10), /* DU1_DG6_Y2_DATA10 */
2681 [11] = RCAR_GP_PIN(1, 11), /* DU1_DG7_Y3_DATA11 */
2682 [12] = RCAR_GP_PIN(1, 12), /* DU1_DB2_C0_DATA12 */
2683 [13] = RCAR_GP_PIN(1, 13), /* DU1_DB3_C1_DATA13 */
2684 [14] = RCAR_GP_PIN(1, 14), /* DU1_DB4_C2_DATA14 */
2685 [15] = RCAR_GP_PIN(1, 15), /* DU1_DB5_C3_DATA15 */
2686 [16] = RCAR_GP_PIN(1, 16), /* DU1_DB6_C4 */
2687 [17] = RCAR_GP_PIN(1, 17), /* DU1_DB7_C5 */
2688 [18] = RCAR_GP_PIN(1, 18), /* DU1_EXHSYNC/DU1_HSYNC */
2689 [19] = RCAR_GP_PIN(1, 19), /* DU1_EXVSYNC/DU1_VSYNC */
2690 [20] = RCAR_GP_PIN(1, 20), /* DU1_EXODDF/DU1_ODDF_DISP_CDE */
2691 [21] = RCAR_GP_PIN(1, 21), /* DU1_DISP */
2692 [22] = RCAR_GP_PIN(1, 22), /* DU1_CDE */
2693 [23] = SH_PFC_PIN_NONE,
2694 [24] = SH_PFC_PIN_NONE,
2695 [25] = SH_PFC_PIN_NONE,
2696 [26] = SH_PFC_PIN_NONE,
2697 [27] = SH_PFC_PIN_NONE,
2698 [28] = SH_PFC_PIN_NONE,
2699 [29] = SH_PFC_PIN_NONE,
2700 [30] = SH_PFC_PIN_NONE,
2701 [31] = SH_PFC_PIN_NONE,
2702 } },
2703 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
2704 [ 0] = RCAR_GP_PIN(2, 0), /* D0 */
2705 [ 1] = RCAR_GP_PIN(2, 1), /* D1 */
2706 [ 2] = RCAR_GP_PIN(2, 2), /* D2 */
2707 [ 3] = RCAR_GP_PIN(2, 3), /* D3 */
2708 [ 4] = RCAR_GP_PIN(2, 4), /* D4 */
2709 [ 5] = RCAR_GP_PIN(2, 5), /* D5 */
2710 [ 6] = RCAR_GP_PIN(2, 6), /* D6 */
2711 [ 7] = RCAR_GP_PIN(2, 7), /* D7 */
2712 [ 8] = RCAR_GP_PIN(2, 8), /* D8 */
2713 [ 9] = RCAR_GP_PIN(2, 9), /* D9 */
2714 [10] = RCAR_GP_PIN(2, 10), /* D10 */
2715 [11] = RCAR_GP_PIN(2, 11), /* D11 */
2716 [12] = RCAR_GP_PIN(2, 12), /* D12 */
2717 [13] = RCAR_GP_PIN(2, 13), /* D13 */
2718 [14] = RCAR_GP_PIN(2, 14), /* D14 */
2719 [15] = RCAR_GP_PIN(2, 15), /* D15 */
2720 [16] = RCAR_GP_PIN(2, 16), /* A0 */
2721 [17] = RCAR_GP_PIN(2, 17), /* A1 */
2722 [18] = RCAR_GP_PIN(2, 18), /* A2 */
2723 [19] = RCAR_GP_PIN(2, 19), /* A3 */
2724 [20] = RCAR_GP_PIN(2, 20), /* A4 */
2725 [21] = RCAR_GP_PIN(2, 21), /* A5 */
2726 [22] = RCAR_GP_PIN(2, 22), /* A6 */
2727 [23] = RCAR_GP_PIN(2, 23), /* A7 */
2728 [24] = RCAR_GP_PIN(2, 24), /* A8 */
2729 [25] = RCAR_GP_PIN(2, 25), /* A9 */
2730 [26] = RCAR_GP_PIN(2, 26), /* A10 */
2731 [27] = RCAR_GP_PIN(2, 27), /* A11 */
2732 [28] = RCAR_GP_PIN(2, 28), /* A12 */
2733 [29] = RCAR_GP_PIN(2, 29), /* A13 */
2734 [30] = RCAR_GP_PIN(2, 30), /* A14 */
2735 [31] = RCAR_GP_PIN(2, 31), /* A15 */
2736 } },
2737 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
2738 [ 0] = RCAR_GP_PIN(3, 0), /* A16 */
2739 [ 1] = RCAR_GP_PIN(3, 1), /* A17 */
2740 [ 2] = RCAR_GP_PIN(3, 2), /* A18 */
2741 [ 3] = RCAR_GP_PIN(3, 3), /* A19 */
2742 [ 4] = RCAR_GP_PIN(3, 4), /* A20 */
2743 [ 5] = RCAR_GP_PIN(3, 5), /* A21 */
2744 [ 6] = RCAR_GP_PIN(3, 6), /* CS1#/A26 */
2745 [ 7] = RCAR_GP_PIN(3, 7), /* EX_CS0# */
2746 [ 8] = RCAR_GP_PIN(3, 8), /* EX_CS1# */
2747 [ 9] = RCAR_GP_PIN(3, 9), /* EX_CS2# */
2748 [10] = RCAR_GP_PIN(3, 10), /* EX_CS3# */
2749 [11] = RCAR_GP_PIN(3, 11), /* EX_CS4# */
2750 [12] = RCAR_GP_PIN(3, 12), /* EX_CS5# */
2751 [13] = RCAR_GP_PIN(3, 13), /* BS# */
2752 [14] = RCAR_GP_PIN(3, 14), /* RD# */
2753 [15] = RCAR_GP_PIN(3, 15), /* RD/WR# */
2754 [16] = RCAR_GP_PIN(3, 16), /* WE0# */
2755 [17] = RCAR_GP_PIN(3, 17), /* WE1# */
2756 [18] = RCAR_GP_PIN(3, 18), /* EX_WAIT0 */
2757 [19] = RCAR_GP_PIN(3, 19), /* IRQ0 */
2758 [20] = RCAR_GP_PIN(3, 20), /* IRQ1 */
2759 [21] = RCAR_GP_PIN(3, 21), /* IRQ2 */
2760 [22] = RCAR_GP_PIN(3, 22), /* IRQ3 */
2761 [23] = RCAR_GP_PIN(3, 23), /* A22 */
2762 [24] = RCAR_GP_PIN(3, 24), /* A23 */
2763 [25] = RCAR_GP_PIN(3, 25), /* A24 */
2764 [26] = RCAR_GP_PIN(3, 26), /* A25 */
2765 [27] = RCAR_GP_PIN(3, 27), /* CS0# */
2766 [28] = SH_PFC_PIN_NONE,
2767 [29] = SH_PFC_PIN_NONE,
2768 [30] = SH_PFC_PIN_NONE,
2769 [31] = SH_PFC_PIN_NONE,
2770 } },
2771 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
2772 [ 0] = RCAR_GP_PIN(4, 0), /* VI0_CLK */
2773 [ 1] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */
2774 [ 2] = RCAR_GP_PIN(4, 2), /* VI0_HSYNC# */
2775 [ 3] = RCAR_GP_PIN(4, 3), /* VI0_VSYNC# */
2776 [ 4] = RCAR_GP_PIN(4, 4), /* VI0_D0_B0_C0 */
2777 [ 5] = RCAR_GP_PIN(4, 5), /* VI0_D1_B1_C1 */
2778 [ 6] = RCAR_GP_PIN(4, 6), /* VI0_D2_B2_C2 */
2779 [ 7] = RCAR_GP_PIN(4, 7), /* VI0_D3_B3_C3 */
2780 [ 8] = RCAR_GP_PIN(4, 8), /* VI0_D4_B4_C4 */
2781 [ 9] = RCAR_GP_PIN(4, 9), /* VI0_D5_B5_C5 */
2782 [10] = RCAR_GP_PIN(4, 10), /* VI0_D6_B6_C6 */
2783 [11] = RCAR_GP_PIN(4, 11), /* VI0_D7_B7_C7 */
2784 [12] = RCAR_GP_PIN(4, 12), /* VI0_D8_G0_Y0 */
2785 [13] = RCAR_GP_PIN(4, 13), /* VI0_D9_G1_Y1 */
2786 [14] = RCAR_GP_PIN(4, 14), /* VI0_D10_G2_Y2 */
2787 [15] = RCAR_GP_PIN(4, 15), /* VI0_D11_G3_Y3 */
2788 [16] = RCAR_GP_PIN(4, 16), /* VI0_FIELD */
2789 [17] = SH_PFC_PIN_NONE,
2790 [18] = SH_PFC_PIN_NONE,
2791 [19] = SH_PFC_PIN_NONE,
2792 [20] = SH_PFC_PIN_NONE,
2793 [21] = SH_PFC_PIN_NONE,
2794 [22] = SH_PFC_PIN_NONE,
2795 [23] = SH_PFC_PIN_NONE,
2796 [24] = SH_PFC_PIN_NONE,
2797 [25] = SH_PFC_PIN_NONE,
2798 [26] = SH_PFC_PIN_NONE,
2799 [27] = SH_PFC_PIN_NONE,
2800 [28] = SH_PFC_PIN_NONE,
2801 [29] = SH_PFC_PIN_NONE,
2802 [30] = SH_PFC_PIN_NONE,
2803 [31] = SH_PFC_PIN_NONE,
2804 } },
2805 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
2806 [ 0] = RCAR_GP_PIN(5, 0), /* VI1_CLK */
2807 [ 1] = RCAR_GP_PIN(5, 1), /* VI1_CLKENB */
2808 [ 2] = RCAR_GP_PIN(5, 2), /* VI1_HSYNC# */
2809 [ 3] = RCAR_GP_PIN(5, 3), /* VI1_VSYNC# */
2810 [ 4] = RCAR_GP_PIN(5, 4), /* VI1_D0_B0_C0 */
2811 [ 5] = RCAR_GP_PIN(5, 5), /* VI1_D1_B1_C1 */
2812 [ 6] = RCAR_GP_PIN(5, 6), /* VI1_D2_B2_C2 */
2813 [ 7] = RCAR_GP_PIN(5, 7), /* VI1_D3_B3_C3 */
2814 [ 8] = RCAR_GP_PIN(5, 8), /* VI1_D4_B4_C4 */
2815 [ 9] = RCAR_GP_PIN(5, 9), /* VI1_D5_B5_C5 */
2816 [10] = RCAR_GP_PIN(5, 10), /* VI1_D6_B6_C6 */
2817 [11] = RCAR_GP_PIN(5, 11), /* VI1_D7_B7_C7 */
2818 [12] = RCAR_GP_PIN(5, 12), /* VI1_D8_G0_Y0 */
2819 [13] = RCAR_GP_PIN(5, 13), /* VI1_D9_G1_Y1 */
2820 [14] = RCAR_GP_PIN(5, 14), /* VI1_D10_G2_Y2 */
2821 [15] = RCAR_GP_PIN(5, 15), /* VI1_D11_G3_Y3 */
2822 [16] = RCAR_GP_PIN(5, 16), /* VI1_FIELD */
2823 [17] = SH_PFC_PIN_NONE,
2824 [18] = SH_PFC_PIN_NONE,
2825 [19] = SH_PFC_PIN_NONE,
2826 [20] = SH_PFC_PIN_NONE,
2827 [21] = SH_PFC_PIN_NONE,
2828 [22] = SH_PFC_PIN_NONE,
2829 [23] = SH_PFC_PIN_NONE,
2830 [24] = SH_PFC_PIN_NONE,
2831 [25] = SH_PFC_PIN_NONE,
2832 [26] = SH_PFC_PIN_NONE,
2833 [27] = SH_PFC_PIN_NONE,
2834 [28] = SH_PFC_PIN_NONE,
2835 [29] = SH_PFC_PIN_NONE,
2836 [30] = SH_PFC_PIN_NONE,
2837 [31] = SH_PFC_PIN_NONE,
2838 } },
2839 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
2840 [ 0] = RCAR_GP_PIN(6, 0), /* VI2_CLK */
2841 [ 1] = RCAR_GP_PIN(6, 1), /* VI2_CLKENB */
2842 [ 2] = RCAR_GP_PIN(6, 2), /* VI2_HSYNC# */
2843 [ 3] = RCAR_GP_PIN(6, 3), /* VI2_VSYNC# */
2844 [ 4] = RCAR_GP_PIN(6, 4), /* VI2_D0_C0 */
2845 [ 5] = RCAR_GP_PIN(6, 5), /* VI2_D1_C1 */
2846 [ 6] = RCAR_GP_PIN(6, 6), /* VI2_D2_C2 */
2847 [ 7] = RCAR_GP_PIN(6, 7), /* VI2_D3_C3 */
2848 [ 8] = RCAR_GP_PIN(6, 8), /* VI2_D4_C4 */
2849 [ 9] = RCAR_GP_PIN(6, 9), /* VI2_D5_C5 */
2850 [10] = RCAR_GP_PIN(6, 10), /* VI2_D6_C6 */
2851 [11] = RCAR_GP_PIN(6, 11), /* VI2_D7_C7 */
2852 [12] = RCAR_GP_PIN(6, 12), /* VI2_D8_Y0 */
2853 [13] = RCAR_GP_PIN(6, 13), /* VI2_D9_Y1 */
2854 [14] = RCAR_GP_PIN(6, 14), /* VI2_D10_Y2 */
2855 [15] = RCAR_GP_PIN(6, 15), /* VI2_D11_Y3 */
2856 [16] = RCAR_GP_PIN(6, 16), /* VI2_FIELD */
2857 [17] = SH_PFC_PIN_NONE,
2858 [18] = SH_PFC_PIN_NONE,
2859 [19] = SH_PFC_PIN_NONE,
2860 [20] = SH_PFC_PIN_NONE,
2861 [21] = SH_PFC_PIN_NONE,
2862 [22] = SH_PFC_PIN_NONE,
2863 [23] = SH_PFC_PIN_NONE,
2864 [24] = SH_PFC_PIN_NONE,
2865 [25] = SH_PFC_PIN_NONE,
2866 [26] = SH_PFC_PIN_NONE,
2867 [27] = SH_PFC_PIN_NONE,
2868 [28] = SH_PFC_PIN_NONE,
2869 [29] = SH_PFC_PIN_NONE,
2870 [30] = SH_PFC_PIN_NONE,
2871 [31] = SH_PFC_PIN_NONE,
2872 } },
2873 { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
2874 [ 0] = RCAR_GP_PIN(7, 0), /* VI3_CLK */
2875 [ 1] = RCAR_GP_PIN(7, 1), /* VI3_CLKENB */
2876 [ 2] = RCAR_GP_PIN(7, 2), /* VI3_HSYNC# */
2877 [ 3] = RCAR_GP_PIN(7, 3), /* VI3_VSYNC# */
2878 [ 4] = RCAR_GP_PIN(7, 4), /* VI3_D0_C0 */
2879 [ 5] = RCAR_GP_PIN(7, 5), /* VI3_D1_C1 */
2880 [ 6] = RCAR_GP_PIN(7, 6), /* VI3_D2_C2 */
2881 [ 7] = RCAR_GP_PIN(7, 7), /* VI3_D3_C3 */
2882 [ 8] = RCAR_GP_PIN(7, 8), /* VI3_D4_C4 */
2883 [ 9] = RCAR_GP_PIN(7, 9), /* VI3_D5_C5 */
2884 [10] = RCAR_GP_PIN(7, 10), /* VI3_D6_C6 */
2885 [11] = RCAR_GP_PIN(7, 11), /* VI3_D7_C7 */
2886 [12] = RCAR_GP_PIN(7, 12), /* VI3_D8_Y0 */
2887 [13] = RCAR_GP_PIN(7, 13), /* VI3_D9_Y1 */
2888 [14] = RCAR_GP_PIN(7, 14), /* VI3_D10_Y2 */
2889 [15] = RCAR_GP_PIN(7, 15), /* VI3_D11_Y3 */
2890 [16] = RCAR_GP_PIN(7, 16), /* VI3_FIELD */
2891 [17] = SH_PFC_PIN_NONE,
2892 [18] = SH_PFC_PIN_NONE,
2893 [19] = SH_PFC_PIN_NONE,
2894 [20] = SH_PFC_PIN_NONE,
2895 [21] = SH_PFC_PIN_NONE,
2896 [22] = SH_PFC_PIN_NONE,
2897 [23] = SH_PFC_PIN_NONE,
2898 [24] = SH_PFC_PIN_NONE,
2899 [25] = SH_PFC_PIN_NONE,
2900 [26] = SH_PFC_PIN_NONE,
2901 [27] = SH_PFC_PIN_NONE,
2902 [28] = SH_PFC_PIN_NONE,
2903 [29] = SH_PFC_PIN_NONE,
2904 [30] = SH_PFC_PIN_NONE,
2905 [31] = SH_PFC_PIN_NONE,
2906 } },
2907 { PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) {
2908 [ 0] = RCAR_GP_PIN(8, 0), /* VI4_CLK */
2909 [ 1] = RCAR_GP_PIN(8, 1), /* VI4_CLKENB */
2910 [ 2] = RCAR_GP_PIN(8, 2), /* VI4_HSYNC# */
2911 [ 3] = RCAR_GP_PIN(8, 3), /* VI4_VSYNC# */
2912 [ 4] = RCAR_GP_PIN(8, 4), /* VI4_D0_C0 */
2913 [ 5] = RCAR_GP_PIN(8, 5), /* VI4_D1_C1 */
2914 [ 6] = RCAR_GP_PIN(8, 6), /* VI4_D2_C2 */
2915 [ 7] = RCAR_GP_PIN(8, 7), /* VI4_D3_C3 */
2916 [ 8] = RCAR_GP_PIN(8, 8), /* VI4_D4_C4 */
2917 [ 9] = RCAR_GP_PIN(8, 9), /* VI4_D5_C5 */
2918 [10] = RCAR_GP_PIN(8, 10), /* VI4_D6_C6 */
2919 [11] = RCAR_GP_PIN(8, 11), /* VI4_D7_C7 */
2920 [12] = RCAR_GP_PIN(8, 12), /* VI4_D8_Y0 */
2921 [13] = RCAR_GP_PIN(8, 13), /* VI4_D9_Y1 */
2922 [14] = RCAR_GP_PIN(8, 14), /* VI4_D10_Y2 */
2923 [15] = RCAR_GP_PIN(8, 15), /* VI4_D11_Y3 */
2924 [16] = RCAR_GP_PIN(8, 16), /* VI4_FIELD */
2925 [17] = SH_PFC_PIN_NONE,
2926 [18] = SH_PFC_PIN_NONE,
2927 [19] = SH_PFC_PIN_NONE,
2928 [20] = SH_PFC_PIN_NONE,
2929 [21] = SH_PFC_PIN_NONE,
2930 [22] = SH_PFC_PIN_NONE,
2931 [23] = SH_PFC_PIN_NONE,
2932 [24] = SH_PFC_PIN_NONE,
2933 [25] = SH_PFC_PIN_NONE,
2934 [26] = SH_PFC_PIN_NONE,
2935 [27] = SH_PFC_PIN_NONE,
2936 [28] = SH_PFC_PIN_NONE,
2937 [29] = SH_PFC_PIN_NONE,
2938 [30] = SH_PFC_PIN_NONE,
2939 [31] = SH_PFC_PIN_NONE,
2940 } },
2941 { PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) {
2942 [ 0] = RCAR_GP_PIN(9, 0), /* VI5_CLK */
2943 [ 1] = RCAR_GP_PIN(9, 1), /* VI5_CLKENB */
2944 [ 2] = RCAR_GP_PIN(9, 2), /* VI5_HSYNC# */
2945 [ 3] = RCAR_GP_PIN(9, 3), /* VI5_VSYNC# */
2946 [ 4] = RCAR_GP_PIN(9, 4), /* VI5_D0_C0 */
2947 [ 5] = RCAR_GP_PIN(9, 5), /* VI5_D1_C1 */
2948 [ 6] = RCAR_GP_PIN(9, 6), /* VI5_D2_C2 */
2949 [ 7] = RCAR_GP_PIN(9, 7), /* VI5_D3_C3 */
2950 [ 8] = RCAR_GP_PIN(9, 8), /* VI5_D4_C4 */
2951 [ 9] = RCAR_GP_PIN(9, 9), /* VI5_D5_C5 */
2952 [10] = RCAR_GP_PIN(9, 10), /* VI5_D6_C6 */
2953 [11] = RCAR_GP_PIN(9, 11), /* VI5_D7_C7 */
2954 [12] = RCAR_GP_PIN(9, 12), /* VI5_D8_Y0 */
2955 [13] = RCAR_GP_PIN(9, 13), /* VI5_D9_Y1 */
2956 [14] = RCAR_GP_PIN(9, 14), /* VI5_D10_Y2 */
2957 [15] = RCAR_GP_PIN(9, 15), /* VI5_D11_Y3 */
2958 [16] = RCAR_GP_PIN(9, 16), /* VI5_FIELD */
2959 [17] = SH_PFC_PIN_NONE,
2960 [18] = SH_PFC_PIN_NONE,
2961 [19] = SH_PFC_PIN_NONE,
2962 [20] = SH_PFC_PIN_NONE,
2963 [21] = SH_PFC_PIN_NONE,
2964 [22] = SH_PFC_PIN_NONE,
2965 [23] = SH_PFC_PIN_NONE,
2966 [24] = SH_PFC_PIN_NONE,
2967 [25] = SH_PFC_PIN_NONE,
2968 [26] = SH_PFC_PIN_NONE,
2969 [27] = SH_PFC_PIN_NONE,
2970 [28] = SH_PFC_PIN_NONE,
2971 [29] = SH_PFC_PIN_NONE,
2972 [30] = SH_PFC_PIN_NONE,
2973 [31] = SH_PFC_PIN_NONE,
2974 } },
2975 { PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) {
2976 [ 0] = RCAR_GP_PIN(10, 0), /* HSCK0 */
2977 [ 1] = RCAR_GP_PIN(10, 1), /* HCTS0# */
2978 [ 2] = RCAR_GP_PIN(10, 2), /* HRTS0# */
2979 [ 3] = RCAR_GP_PIN(10, 3), /* HTX0 */
2980 [ 4] = RCAR_GP_PIN(10, 4), /* HRX0 */
2981 [ 5] = RCAR_GP_PIN(10, 5), /* HSCK1 */
2982 [ 6] = RCAR_GP_PIN(10, 6), /* HRTS1# */
2983 [ 7] = RCAR_GP_PIN(10, 7), /* HCTS1# */
2984 [ 8] = RCAR_GP_PIN(10, 8), /* HTX1 */
2985 [ 9] = RCAR_GP_PIN(10, 9), /* HRX1 */
2986 [10] = RCAR_GP_PIN(10, 10), /* SCK0 */
2987 [11] = RCAR_GP_PIN(10, 11), /* CTS0# */
2988 [12] = RCAR_GP_PIN(10, 12), /* RTS0# */
2989 [13] = RCAR_GP_PIN(10, 13), /* TX0 */
2990 [14] = RCAR_GP_PIN(10, 14), /* RX0 */
2991 [15] = RCAR_GP_PIN(10, 15), /* SCK1 */
2992 [16] = RCAR_GP_PIN(10, 16), /* CTS1# */
2993 [17] = RCAR_GP_PIN(10, 17), /* RTS1# */
2994 [18] = RCAR_GP_PIN(10, 18), /* TX1 */
2995 [19] = RCAR_GP_PIN(10, 19), /* RX1 */
2996 [20] = RCAR_GP_PIN(10, 20), /* SCK2 */
2997 [21] = RCAR_GP_PIN(10, 21), /* TX2 */
2998 [22] = RCAR_GP_PIN(10, 22), /* RX2 */
2999 [23] = RCAR_GP_PIN(10, 23), /* SCK3 */
3000 [24] = RCAR_GP_PIN(10, 24), /* TX3 */
3001 [25] = RCAR_GP_PIN(10, 25), /* RX3 */
3002 [26] = RCAR_GP_PIN(10, 26), /* SCIF_CLK */
3003 [27] = RCAR_GP_PIN(10, 27), /* CAN0_TX */
3004 [28] = RCAR_GP_PIN(10, 28), /* CAN0_RX */
3005 [29] = RCAR_GP_PIN(10, 29), /* CAN_CLK */
3006 [30] = RCAR_GP_PIN(10, 30), /* CAN1_TX */
3007 [31] = RCAR_GP_PIN(10, 31), /* CAN1_RX */
3008 } },
3009 { PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) {
3010 [ 0] = RCAR_GP_PIN(11, 0), /* PWM0 */
3011 [ 1] = RCAR_GP_PIN(11, 1), /* PWM1 */
3012 [ 2] = RCAR_GP_PIN(11, 2), /* PWM2 */
3013 [ 3] = RCAR_GP_PIN(11, 3), /* PWM3 */
3014 [ 4] = RCAR_GP_PIN(11, 4), /* PWM4 */
3015 [ 5] = RCAR_GP_PIN(11, 5), /* SD0_CLK */
3016 [ 6] = RCAR_GP_PIN(11, 6), /* SD0_CMD */
3017 [ 7] = RCAR_GP_PIN(11, 7), /* SD0_DAT0 */
3018 [ 8] = RCAR_GP_PIN(11, 8), /* SD0_DAT1 */
3019 [ 9] = RCAR_GP_PIN(11, 9), /* SD0_DAT2 */
3020 [10] = RCAR_GP_PIN(11, 10), /* SD0_DAT3 */
3021 [11] = RCAR_GP_PIN(11, 11), /* SD0_CD */
3022 [12] = RCAR_GP_PIN(11, 12), /* SD0_WP */
3023 [13] = RCAR_GP_PIN(11, 13), /* SSI_SCK3 */
3024 [14] = RCAR_GP_PIN(11, 14), /* SSI_WS3 */
3025 [15] = RCAR_GP_PIN(11, 15), /* SSI_SDATA3 */
3026 [16] = RCAR_GP_PIN(11, 16), /* SSI_SCK4 */
3027 [17] = RCAR_GP_PIN(11, 17), /* SSI_WS4 */
3028 [18] = RCAR_GP_PIN(11, 18), /* SSI_SDATA4 */
3029 [19] = RCAR_GP_PIN(11, 19), /* AUDIO_CLKOUT */
3030 [20] = RCAR_GP_PIN(11, 20), /* AUDIO_CLKA */
3031 [21] = RCAR_GP_PIN(11, 21), /* AUDIO_CLKB */
3032 [22] = RCAR_GP_PIN(11, 22), /* ADICLK */
3033 [23] = RCAR_GP_PIN(11, 23), /* ADICS_SAMP */
3034 [24] = RCAR_GP_PIN(11, 24), /* ADIDATA */
3035 [25] = RCAR_GP_PIN(11, 25), /* ADICHS0 */
3036 [26] = RCAR_GP_PIN(11, 26), /* ADICHS1 */
3037 [27] = RCAR_GP_PIN(11, 27), /* ADICHS2 */
3038 [28] = RCAR_GP_PIN(11, 28), /* AVS1 */
3039 [29] = RCAR_GP_PIN(11, 29), /* AVS2 */
3040 [30] = SH_PFC_PIN_NONE,
3041 [31] = SH_PFC_PIN_NONE,
3042 } },
3043 { PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) {
3044 /* PUPR12 pull-up pins */
3045 [ 0] = PIN_DU0_DOTCLKIN, /* DU0_DOTCLKIN */
3046 [ 1] = PIN_DU0_DOTCLKOUT, /* DU0_DOTCLKOUT */
3047 [ 2] = PIN_DU1_DOTCLKIN, /* DU1_DOTCLKIN */
3048 [ 3] = PIN_DU1_DOTCLKOUT, /* DU1_DOTCLKOUT */
3049 [ 4] = PIN_TRST_N, /* TRST# */
3050 [ 5] = PIN_TCK, /* TCK */
3051 [ 6] = PIN_TMS, /* TMS */
3052 [ 7] = PIN_TDI, /* TDI */
3053 [ 8] = SH_PFC_PIN_NONE,
3054 [ 9] = SH_PFC_PIN_NONE,
3055 [10] = SH_PFC_PIN_NONE,
3056 [11] = SH_PFC_PIN_NONE,
3057 [12] = SH_PFC_PIN_NONE,
3058 [13] = SH_PFC_PIN_NONE,
3059 [14] = SH_PFC_PIN_NONE,
3060 [15] = SH_PFC_PIN_NONE,
3061 [16] = SH_PFC_PIN_NONE,
3062 [17] = SH_PFC_PIN_NONE,
3063 [18] = SH_PFC_PIN_NONE,
3064 [19] = SH_PFC_PIN_NONE,
3065 [20] = SH_PFC_PIN_NONE,
3066 [21] = SH_PFC_PIN_NONE,
3067 [22] = SH_PFC_PIN_NONE,
3068 [23] = SH_PFC_PIN_NONE,
3069 [24] = SH_PFC_PIN_NONE,
3070 [25] = SH_PFC_PIN_NONE,
3071 [26] = SH_PFC_PIN_NONE,
3072 [27] = SH_PFC_PIN_NONE,
3073 [28] = SH_PFC_PIN_NONE,
3074 [29] = SH_PFC_PIN_NONE,
3075 [30] = SH_PFC_PIN_NONE,
3076 [31] = SH_PFC_PIN_NONE,
3077 } },
3078 { PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) {
3079 /* PUPR12 pull-down pins */
3080 [ 0] = SH_PFC_PIN_NONE,
3081 [ 1] = SH_PFC_PIN_NONE,
3082 [ 2] = SH_PFC_PIN_NONE,
3083 [ 3] = SH_PFC_PIN_NONE,
3084 [ 4] = SH_PFC_PIN_NONE,
3085 [ 5] = SH_PFC_PIN_NONE,
3086 [ 6] = SH_PFC_PIN_NONE,
3087 [ 7] = SH_PFC_PIN_NONE,
3088 [ 8] = PIN_EDBGREQ, /* EDBGREQ */
3089 [ 9] = SH_PFC_PIN_NONE,
3090 [10] = SH_PFC_PIN_NONE,
3091 [11] = SH_PFC_PIN_NONE,
3092 [12] = SH_PFC_PIN_NONE,
3093 [13] = SH_PFC_PIN_NONE,
3094 [14] = SH_PFC_PIN_NONE,
3095 [15] = SH_PFC_PIN_NONE,
3096 [16] = SH_PFC_PIN_NONE,
3097 [17] = SH_PFC_PIN_NONE,
3098 [18] = SH_PFC_PIN_NONE,
3099 [19] = SH_PFC_PIN_NONE,
3100 [20] = SH_PFC_PIN_NONE,
3101 [21] = SH_PFC_PIN_NONE,
3102 [22] = SH_PFC_PIN_NONE,
3103 [23] = SH_PFC_PIN_NONE,
3104 [24] = SH_PFC_PIN_NONE,
3105 [25] = SH_PFC_PIN_NONE,
3106 [26] = SH_PFC_PIN_NONE,
3107 [27] = SH_PFC_PIN_NONE,
3108 [28] = SH_PFC_PIN_NONE,
3109 [29] = SH_PFC_PIN_NONE,
3110 [30] = SH_PFC_PIN_NONE,
3111 [31] = SH_PFC_PIN_NONE,
3112 } },
3113 { /* sentinel */ }
3114};
3115
3116static const struct sh_pfc_soc_operations r8a7792_pfc_ops = {
3117 .get_bias = rcar_pinmux_get_bias,
3118 .set_bias = rcar_pinmux_set_bias,
3119};
3120
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]3121const struct sh_pfc_soc_info r8a7792_pinmux_info = {
3122 .name = "r8a77920_pfc",
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]3123 .ops = &r8a7792_pfc_ops,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]3124 .unlock_reg = 0xe6060000, /* PMMR */
3125
3126 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3127
3128 .pins = pinmux_pins,
3129 .nr_pins = ARRAY_SIZE(pinmux_pins),
3130 .groups = pinmux_groups,
3131 .nr_groups = ARRAY_SIZE(pinmux_groups),
3132 .functions = pinmux_functions,
3133 .nr_functions = ARRAY_SIZE(pinmux_functions),
3134
3135 .cfg_regs = pinmux_config_regs,
Marek Vasutab945d32023-01-26 21:01:38 +0100[diff] [blame]3136 .bias_regs = pinmux_bias_regs,
Marek Vasut1ef39302018-01-17 22:29:50 +0100[diff] [blame]3137
3138 .pinmux_data = pinmux_data,
3139 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3140};