blob: 902d1a51eaa3e819883e0c63f001cfb5a1399a56 [file] [log] [blame]
Ramon Fried663686d2019-04-27 11:15:21 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PCI Endpoint uclass
4 *
5 * Based on Linux PCI-EP driver written by
6 * Kishon Vijay Abraham I <kishon@ti.com>
7 *
8 * Copyright (c) 2019
9 * Written by Ramon Fried <ramon.fried@gmail.com>
10 */
11
Patrick Delaunay81313352021-04-27 11:02:19 +020012#define LOG_CATEGORY UCLASS_PCI_EP
13
Ramon Fried663686d2019-04-27 11:15:21 +030014#include <dm.h>
15#include <errno.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
Ramon Fried663686d2019-04-27 11:15:21 +030017#include <linux/log2.h>
18#include <pci_ep.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
23{
24 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
25
26 if (!ops->write_header)
27 return -ENOSYS;
28
29 return ops->write_header(dev, fn, hdr);
30}
31
32int pci_ep_read_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
33{
34 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
35
36 if (!ops->read_header)
37 return -ENOSYS;
38
39 return ops->read_header(dev, fn, hdr);
40}
41
42int pci_ep_set_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar)
43{
44 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
45 int flags = ep_bar->flags;
46
47 /* Some basic bar validity checks */
Ramon Fried77990812019-07-31 11:04:26 +030048 if (ep_bar->barno > BAR_5 || ep_bar->barno < BAR_0)
Ramon Fried663686d2019-04-27 11:15:21 +030049 return -EINVAL;
50
51 if ((ep_bar->barno == BAR_5 &&
52 (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) ||
53 ((flags & PCI_BASE_ADDRESS_SPACE_IO) &&
54 (flags & PCI_BASE_ADDRESS_IO_MASK)) ||
55 (upper_32_bits(ep_bar->size) &&
56 !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
57 return -EINVAL;
58
59 if (!ops->set_bar)
60 return -ENOSYS;
61
62 return ops->set_bar(dev, func_no, ep_bar);
63}
64
65int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
66 enum pci_barno barno)
67{
68 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
69
70 /* Some basic bar validity checks */
71 if (barno > BAR_5 || barno < BAR_0)
72 return -EINVAL;
73
74 if (!ops->read_bar)
75 return -ENOSYS;
76
77 return ops->read_bar(dev, func_no, ep_bar, barno);
78}
79
80int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar)
81{
82 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
83
84 if (!ops->clear_bar)
85 return -ENOSYS;
86
87 return ops->clear_bar(dev, func_num, bar);
88}
89
90int pci_ep_map_addr(struct udevice *dev, uint func_no, phys_addr_t addr,
91 u64 pci_addr, size_t size)
92{
93 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
94
95 if (!ops->map_addr)
96 return -ENOSYS;
97
98 return ops->map_addr(dev, func_no, addr, pci_addr, size);
99}
100
101int pci_ep_unmap_addr(struct udevice *dev, uint func_no, phys_addr_t addr)
102{
103 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
104
105 if (!ops->unmap_addr)
106 return -ENOSYS;
107
108 return ops->unmap_addr(dev, func_no, addr);
109}
110
111int pci_ep_set_msi(struct udevice *dev, uint func_no, uint interrupts)
112{
113 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
114 uint encode_int;
115
116 if (interrupts > 32)
117 return -EINVAL;
118
119 if (!ops->set_msi)
120 return -ENOSYS;
121
122 /* MSI spec permits allocation of
123 * only 1, 2, 4, 8, 16, 32 interrupts
124 */
125 encode_int = order_base_2(interrupts);
126
127 return ops->set_msi(dev, func_no, encode_int);
128}
129
130int pci_ep_get_msi(struct udevice *dev, uint func_no)
131{
132 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
133 int interrupt;
134
135 if (!ops->get_msi)
136 return -ENOSYS;
137
138 interrupt = ops->get_msi(dev, func_no);
139
140 if (interrupt < 0)
141 return 0;
142
143 /* Translate back from order base 2*/
144 interrupt = 1 << interrupt;
145
146 return interrupt;
147}
148
149int pci_ep_set_msix(struct udevice *dev, uint func_no, uint interrupts)
150{
151 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
152
153 if (interrupts < 1 || interrupts > 2048)
154 return -EINVAL;
155
156 if (!ops->set_msix)
157 return -ENOSYS;
158
159 return ops->set_msix(dev, func_no, interrupts - 1);
160}
161
162int pci_ep_get_msix(struct udevice *dev, uint func_no)
163{
164 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
165 int interrupt;
166
167 if (!ops->get_msix)
168 return -ENOSYS;
169
170 interrupt = ops->get_msix(dev, func_no);
171
172 if (interrupt < 0)
173 return 0;
174
175 return interrupt + 1;
176}
177
178int pci_ep_raise_irq(struct udevice *dev, uint func_no,
179 enum pci_ep_irq_type type, uint interrupt_num)
180{
181 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
182
183 if (!ops->raise_irq)
184 return -ENOSYS;
185
186 return ops->raise_irq(dev, func_no, type, interrupt_num);
187}
188
189int pci_ep_start(struct udevice *dev)
190{
191 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
192
193 if (!ops->start)
194 return -ENOSYS;
195
196 return ops->start(dev);
197}
198
199int pci_ep_stop(struct udevice *dev)
200{
201 struct pci_ep_ops *ops = pci_ep_get_ops(dev);
202
203 if (!ops->stop)
204 return -ENOSYS;
205
206 return ops->stop(dev);
207}
208
209UCLASS_DRIVER(pci_ep) = {
210 .id = UCLASS_PCI_EP,
211 .name = "pci_ep",
212 .flags = DM_UC_FLAG_SEQ_ALIAS,
213};
Xiaowei Bao97434b42020-07-09 23:31:34 +0800214
Ovidiu Panaita45c6e12020-11-28 10:43:11 +0200215int pci_ep_init(void)
Xiaowei Bao97434b42020-07-09 23:31:34 +0800216{
217 struct udevice *dev;
218
219 for (uclass_first_device_check(UCLASS_PCI_EP, &dev);
220 dev;
221 uclass_next_device_check(&dev)) {
222 ;
223 }
Ovidiu Panaita45c6e12020-11-28 10:43:11 +0200224
225 return 0;
Xiaowei Bao97434b42020-07-09 23:31:34 +0800226}