blob: d4abc9a041102c584bdcec57280112e9c4acf079 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -04002/*
3 * Ethernet driver for TI K2HK EVM.
4 *
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -04007 */
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -04008#include <command.h>
Simon Glassa73bda42015-11-08 23:47:45 -07009#include <console.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/global_data.h>
Simon Glassdbd79542020-05-10 11:40:11 -060011#include <linux/delay.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060012#include <linux/printk.h>
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040013
Mugunthan V Nc8386732016-02-02 15:51:33 +053014#include <dm.h>
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +053015#include <dm/lists.h>
Mugunthan V Nc8386732016-02-02 15:51:33 +053016
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040017#include <net.h>
Khoronzhuk, Ivan39cd9f02014-10-17 20:44:35 +030018#include <phy.h>
Khoronzhuk, Ivan2b17d3a2014-10-17 21:01:15 +030019#include <errno.h>
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040020#include <miiphy.h>
21#include <malloc.h>
Khoronzhuk, Ivan7954b862014-09-05 19:02:47 +030022#include <asm/ti-common/keystone_nav.h>
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030023#include <asm/ti-common/keystone_net.h>
Khoronzhuk, Ivandbfecb22014-10-22 17:18:21 +030024#include <asm/ti-common/keystone_serdes.h>
Mugunthan V Nc8386732016-02-02 15:51:33 +053025#include <asm/arch/psc_defs.h>
26
Grygorii Strashkoa2c2e4a2018-10-31 16:21:45 -050027#include "cpsw_mdio.h"
28
Mugunthan V Nc8386732016-02-02 15:51:33 +053029DECLARE_GLOBAL_DATA_PTR;
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040030
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040031#ifdef KEYSTONE2_EMAC_GIG_ENABLE
32#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
33#else
34#define emac_gigabit_enable(x) /* no gigabit to enable */
35#endif
36
37#define RX_BUFF_NUMS 24
38#define RX_BUFF_LEN 1520
39#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
Khoronzhuk, Ivan2b17d3a2014-10-17 21:01:15 +030040#define SGMII_ANEG_TIMEOUT 4000
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040041
42static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
43
Mugunthan V Nc8386732016-02-02 15:51:33 +053044enum link_type {
Mugunthan V N17819112016-08-11 20:04:03 +053045 LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
46 LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
47 LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
48 LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
49 LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
50 LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
51 LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
52 LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
53 LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
54 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
Mugunthan V Nc8386732016-02-02 15:51:33 +053055};
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040056
Mugunthan V Nc8386732016-02-02 15:51:33 +053057#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
58 ((mac)[2] << 16) | ((mac)[3] << 24))
59#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040060
Mugunthan V Nc8386732016-02-02 15:51:33 +053061#ifdef CONFIG_KSNET_NETCP_V1_0
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040062
Mugunthan V Nc8386732016-02-02 15:51:33 +053063#define EMAC_EMACSW_BASE_OFS 0x90800
64#define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
65
66/* CPSW Switch slave registers */
67#define CPGMACSL_REG_SA_LO 0x10
68#define CPGMACSL_REG_SA_HI 0x14
69
70#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
71 (x) * 0x30)
72
Grygorii Strashko6519ea62018-10-31 16:21:41 -050073#elif defined(CONFIG_KSNET_NETCP_V1_5)
Mugunthan V Nc8386732016-02-02 15:51:33 +053074
75#define EMAC_EMACSW_PORT_BASE_OFS 0x222000
76
77/* CPSW Switch slave registers */
78#define CPGMACSL_REG_SA_LO 0x308
79#define CPGMACSL_REG_SA_HI 0x30c
80
81#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
82 (x) * 0x1000)
83
84#endif
85
Mugunthan V Nc8386732016-02-02 15:51:33 +053086struct ks2_eth_priv {
87 struct udevice *dev;
88 struct phy_device *phydev;
89 struct mii_dev *mdio_bus;
90 int phy_addr;
91 phy_interface_t phy_if;
Marek Behún1d371f32022-04-11 21:20:54 +020092 ofnode phy_ofnode;
Mugunthan V Nc8386732016-02-02 15:51:33 +053093 int sgmii_link_type;
Marek Behún6f897ec2022-04-11 21:20:55 +020094 phys_addr_t mdio_base;
Mugunthan V Nc8386732016-02-02 15:51:33 +053095 struct rx_buff_desc net_rx_buffs;
96 struct pktdma_cfg *netcp_pktdma;
97 void *hd;
98 int slave_port;
99 enum link_type link_type;
100 bool emac_open;
101 bool has_mdio;
102};
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400103
Mugunthan V Nc8386732016-02-02 15:51:33 +0530104static void __attribute__((unused))
105 keystone2_eth_gigabit_enable(struct udevice *dev)
106{
107 struct ks2_eth_priv *priv = dev_get_priv(dev);
Mugunthan V Nc8386732016-02-02 15:51:33 +0530108
109 /*
110 * Check if link detected is giga-bit
111 * If Gigabit mode detected, enable gigbit in MAC
112 */
Grygorii Strashkoa2c2e4a2018-10-31 16:21:45 -0500113 if (priv->has_mdio) {
114 if (priv->phydev->speed != 1000)
115 return;
116 }
117
Mugunthan V Nc8386732016-02-02 15:51:33 +0530118 writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
119 CPGMACSL_REG_CTL) |
120 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
121 DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
122}
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400123
Vitaly Andrianov4cedef32015-09-19 16:26:50 +0530124#ifdef CONFIG_SOC_K2G
125int keystone_rgmii_config(struct phy_device *phy_dev)
126{
127 unsigned int i, status;
128
129 i = 0;
130 do {
131 if (i > SGMII_ANEG_TIMEOUT) {
132 puts(" TIMEOUT !\n");
133 phy_dev->link = 0;
134 return 0;
135 }
136
137 if (ctrlc()) {
138 puts("user interrupt!\n");
139 phy_dev->link = 0;
140 return -EINTR;
141 }
142
143 if ((i++ % 500) == 0)
144 printf(".");
145
146 udelay(1000); /* 1 ms */
147 status = readl(RGMII_STATUS_REG);
148 } while (!(status & RGMII_REG_STATUS_LINK));
149
150 puts(" done\n");
151
152 return 0;
153}
154#else
Khoronzhuk, Ivan2b17d3a2014-10-17 21:01:15 +0300155int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400156{
157 unsigned int i, status, mask;
158 unsigned int mr_adv_ability, control;
159
160 switch (interface) {
161 case SGMII_LINK_MAC_MAC_AUTONEG:
162 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
163 SGMII_REG_MR_ADV_LINK |
164 SGMII_REG_MR_ADV_FULL_DUPLEX |
165 SGMII_REG_MR_ADV_GIG_MODE);
166 control = (SGMII_REG_CONTROL_MASTER |
167 SGMII_REG_CONTROL_AUTONEG);
168
169 break;
170 case SGMII_LINK_MAC_PHY:
171 case SGMII_LINK_MAC_PHY_FORCED:
172 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
173 control = SGMII_REG_CONTROL_AUTONEG;
174
175 break;
176 case SGMII_LINK_MAC_MAC_FORCED:
177 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
178 SGMII_REG_MR_ADV_LINK |
179 SGMII_REG_MR_ADV_FULL_DUPLEX |
180 SGMII_REG_MR_ADV_GIG_MODE);
181 control = SGMII_REG_CONTROL_MASTER;
182
183 break;
184 case SGMII_LINK_MAC_FIBER:
185 mr_adv_ability = 0x20;
186 control = SGMII_REG_CONTROL_AUTONEG;
187
188 break;
189 default:
190 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
191 control = SGMII_REG_CONTROL_AUTONEG;
192 }
193
194 __raw_writel(0, SGMII_CTL_REG(port));
195
196 /*
197 * Wait for the SerDes pll to lock,
198 * but don't trap if lock is never read
199 */
200 for (i = 0; i < 1000; i++) {
201 udelay(2000);
202 status = __raw_readl(SGMII_STATUS_REG(port));
203 if ((status & SGMII_REG_STATUS_LOCK) != 0)
204 break;
205 }
206
207 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
208 __raw_writel(control, SGMII_CTL_REG(port));
209
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400210 mask = SGMII_REG_STATUS_LINK;
211
212 if (control & SGMII_REG_CONTROL_AUTONEG)
213 mask |= SGMII_REG_STATUS_AUTONEG;
214
Khoronzhuk, Ivan2b17d3a2014-10-17 21:01:15 +0300215 status = __raw_readl(SGMII_STATUS_REG(port));
216 if ((status & mask) == mask)
217 return 0;
218
219 printf("\n%s Waiting for SGMII auto negotiation to complete",
220 phy_dev->dev->name);
221 while ((status & mask) != mask) {
222 /*
223 * Timeout reached ?
224 */
225 if (i > SGMII_ANEG_TIMEOUT) {
226 puts(" TIMEOUT !\n");
227 phy_dev->link = 0;
228 return 0;
229 }
230
231 if (ctrlc()) {
232 puts("user interrupt!\n");
233 phy_dev->link = 0;
234 return -EINTR;
235 }
236
237 if ((i++ % 500) == 0)
238 printf(".");
239
240 udelay(1000); /* 1 ms */
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400241 status = __raw_readl(SGMII_STATUS_REG(port));
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400242 }
Khoronzhuk, Ivan2b17d3a2014-10-17 21:01:15 +0300243 puts(" done\n");
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400244
245 return 0;
246}
Vitaly Andrianov4cedef32015-09-19 16:26:50 +0530247#endif
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400248
249int mac_sl_reset(u32 port)
250{
251 u32 i, v;
252
253 if (port >= DEVICE_N_GMACSL_PORTS)
254 return GMACSL_RET_INVALID_PORT;
255
256 /* Set the soft reset bit */
Khoronzhuk, Ivan49d39a22014-08-28 16:07:45 +0300257 writel(CPGMAC_REG_RESET_VAL_RESET,
258 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400259
260 /* Wait for the bit to clear */
261 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
Khoronzhuk, Ivan49d39a22014-08-28 16:07:45 +0300262 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400263 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
264 CPGMAC_REG_RESET_VAL_RESET)
265 return GMACSL_RET_OK;
266 }
267
268 /* Timeout on the reset */
269 return GMACSL_RET_WARN_RESET_INCOMPLETE;
270}
271
272int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
273{
274 u32 v, i;
275 int ret = GMACSL_RET_OK;
276
277 if (port >= DEVICE_N_GMACSL_PORTS)
278 return GMACSL_RET_INVALID_PORT;
279
280 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
281 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
282 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
283 }
284
285 /* Must wait if the device is undergoing reset */
286 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
Khoronzhuk, Ivan49d39a22014-08-28 16:07:45 +0300287 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400288 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
289 CPGMAC_REG_RESET_VAL_RESET)
290 break;
291 }
292
293 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
294 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
295
Khoronzhuk, Ivan49d39a22014-08-28 16:07:45 +0300296 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
297 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400298
Vitaly Andrianov4cedef32015-09-19 16:26:50 +0530299#ifndef CONFIG_SOC_K2HK
Khoronzhuk, Ivana7894b72014-10-17 21:01:14 +0300300 /* Map RX packet flow priority to 0 */
301 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
302#endif
303
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400304 return ret;
305}
306
307int ethss_config(u32 ctl, u32 max_pkt_size)
308{
309 u32 i;
310
311 /* Max length register */
Khoronzhuk, Ivan49d39a22014-08-28 16:07:45 +0300312 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400313
314 /* Control register */
Khoronzhuk, Ivan49d39a22014-08-28 16:07:45 +0300315 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400316
317 /* All statistics enabled by default */
Khoronzhuk, Ivan49d39a22014-08-28 16:07:45 +0300318 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
319 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400320
321 /* Reset and enable the ALE */
Khoronzhuk, Ivan49d39a22014-08-28 16:07:45 +0300322 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
323 CPSW_REG_VAL_ALE_CTL_BYPASS,
324 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400325
326 /* All ports put into forward mode */
327 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
Khoronzhuk, Ivan49d39a22014-08-28 16:07:45 +0300328 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
329 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400330
331 return 0;
332}
333
334int ethss_start(void)
335{
336 int i;
337 struct mac_sl_cfg cfg;
338
339 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
340 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
341
342 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
343 mac_sl_reset(i);
344 mac_sl_config(i, &cfg);
345 }
346
347 return 0;
348}
349
350int ethss_stop(void)
351{
352 int i;
353
354 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
355 mac_sl_reset(i);
356
357 return 0;
358}
359
Mugunthan V Nc8386732016-02-02 15:51:33 +0530360struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
361 .clk = SERDES_CLOCK_156P25M,
362 .rate = SERDES_RATE_5G,
363 .rate_mode = SERDES_QUARTER_RATE,
364 .intf = SERDES_PHY_SGMII,
365 .loopback = 0,
366};
367
368#ifndef CONFIG_SOC_K2G
369static void keystone2_net_serdes_setup(void)
370{
Tom Rinic71cb122022-12-04 10:04:30 -0500371 ks2_serdes_init(CFG_KSNET_SERDES_SGMII_BASE,
Mugunthan V Nc8386732016-02-02 15:51:33 +0530372 &ks2_serdes_sgmii_156p25mhz,
Tom Rinifd130b82022-12-04 10:04:28 -0500373 CFG_KSNET_SERDES_LANES_PER_SGMII);
Mugunthan V Nc8386732016-02-02 15:51:33 +0530374
375#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
Tom Rinic2e481e2022-12-04 10:04:29 -0500376 ks2_serdes_init(CFG_KSNET_SERDES_SGMII2_BASE,
Mugunthan V Nc8386732016-02-02 15:51:33 +0530377 &ks2_serdes_sgmii_156p25mhz,
Tom Rinifd130b82022-12-04 10:04:28 -0500378 CFG_KSNET_SERDES_LANES_PER_SGMII);
Mugunthan V Nc8386732016-02-02 15:51:33 +0530379#endif
380
381 /* wait till setup */
382 udelay(5000);
383}
Vitaly Andrianov4cedef32015-09-19 16:26:50 +0530384#endif
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400385
Mugunthan V Nc8386732016-02-02 15:51:33 +0530386static int ks2_eth_start(struct udevice *dev)
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400387{
Mugunthan V Nc8386732016-02-02 15:51:33 +0530388 struct ks2_eth_priv *priv = dev_get_priv(dev);
Hao Zhangd890dff2014-10-22 17:18:23 +0300389
Mugunthan V Nc8386732016-02-02 15:51:33 +0530390#ifdef CONFIG_SOC_K2G
391 keystone_rgmii_config(priv->phydev);
392#else
393 keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
394 priv->sgmii_link_type);
Khoronzhuk, Ivan3df3e632014-10-17 21:01:13 +0300395#endif
396
Mugunthan V Nc8386732016-02-02 15:51:33 +0530397 udelay(10000);
398
399 /* On chip switch configuration */
400 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
401
402 qm_init();
403
404 if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900405 pr_err("ksnav_init failed\n");
Mugunthan V Nc8386732016-02-02 15:51:33 +0530406 goto err_knav_init;
407 }
408
409 /*
410 * Streaming switch configuration. If not present this
411 * statement is defined to void in target.h.
412 * If present this is usually defined to a series of register writes
413 */
414 hw_config_streaming_switch();
415
416 if (priv->has_mdio) {
417 phy_startup(priv->phydev);
418 if (priv->phydev->link == 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900419 pr_err("phy startup failed\n");
Mugunthan V Nc8386732016-02-02 15:51:33 +0530420 goto err_phy_start;
421 }
422 }
423
424 emac_gigabit_enable(dev);
425
426 ethss_start();
427
428 priv->emac_open = true;
429
430 return 0;
431
432err_phy_start:
433 ksnav_close(priv->netcp_pktdma);
434err_knav_init:
435 qm_close();
436
437 return -EFAULT;
438}
439
440static int ks2_eth_send(struct udevice *dev, void *packet, int length)
441{
442 struct ks2_eth_priv *priv = dev_get_priv(dev);
443
444 genphy_update_link(priv->phydev);
445 if (priv->phydev->link == 0)
446 return -1;
447
448 if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
449 length = EMAC_MIN_ETHERNET_PKT_SIZE;
450
451 return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
452 length, (priv->slave_port) << 16);
453}
454
455static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
456{
457 struct ks2_eth_priv *priv = dev_get_priv(dev);
458 int pkt_size;
459 u32 *pkt = NULL;
460
461 priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
462 if (priv->hd == NULL)
463 return -EAGAIN;
464
465 *packetp = (uchar *)pkt;
466
467 return pkt_size;
468}
469
470static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
471 int length)
472{
473 struct ks2_eth_priv *priv = dev_get_priv(dev);
474
475 ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
476
477 return 0;
478}
479
480static void ks2_eth_stop(struct udevice *dev)
481{
482 struct ks2_eth_priv *priv = dev_get_priv(dev);
483
484 if (!priv->emac_open)
485 return;
486 ethss_stop();
487
488 ksnav_close(priv->netcp_pktdma);
489 qm_close();
490 phy_shutdown(priv->phydev);
491 priv->emac_open = false;
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -0400492}
Mugunthan V Nc8386732016-02-02 15:51:33 +0530493
494int ks2_eth_read_rom_hwaddr(struct udevice *dev)
495{
496 struct ks2_eth_priv *priv = dev_get_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700497 struct eth_pdata *pdata = dev_get_plat(dev);
Mugunthan V Nc8386732016-02-02 15:51:33 +0530498 u32 maca = 0;
499 u32 macb = 0;
500
501 /* Read the e-fuse mac address */
502 if (priv->slave_port == 1) {
503 maca = __raw_readl(MAC_ID_BASE_ADDR);
504 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
505 }
506
507 pdata->enetaddr[0] = (macb >> 8) & 0xff;
508 pdata->enetaddr[1] = (macb >> 0) & 0xff;
509 pdata->enetaddr[2] = (maca >> 24) & 0xff;
510 pdata->enetaddr[3] = (maca >> 16) & 0xff;
511 pdata->enetaddr[4] = (maca >> 8) & 0xff;
512 pdata->enetaddr[5] = (maca >> 0) & 0xff;
513
514 return 0;
515}
516
517int ks2_eth_write_hwaddr(struct udevice *dev)
518{
519 struct ks2_eth_priv *priv = dev_get_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700520 struct eth_pdata *pdata = dev_get_plat(dev);
Mugunthan V Nc8386732016-02-02 15:51:33 +0530521
522 writel(mac_hi(pdata->enetaddr),
523 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
524 CPGMACSL_REG_SA_HI);
525 writel(mac_lo(pdata->enetaddr),
526 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
527 CPGMACSL_REG_SA_LO);
528
529 return 0;
530}
531
532static int ks2_eth_probe(struct udevice *dev)
533{
534 struct ks2_eth_priv *priv = dev_get_priv(dev);
535 struct mii_dev *mdio_bus;
Mugunthan V Nc8386732016-02-02 15:51:33 +0530536
537 priv->dev = dev;
Grygorii Strashkoa2c2e4a2018-10-31 16:21:45 -0500538 priv->emac_open = false;
Mugunthan V Nc8386732016-02-02 15:51:33 +0530539
540 /* These clock enables has to be moved to common location */
541 if (cpu_is_k2g())
542 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
543
544 /* By default, select PA PLL clock as PA clock source */
545#ifndef CONFIG_SOC_K2G
546 if (psc_enable_module(KS2_LPSC_PA))
547 return -EACCES;
548#endif
549 if (psc_enable_module(KS2_LPSC_CPGMAC))
550 return -EACCES;
551 if (psc_enable_module(KS2_LPSC_CRYPTO))
552 return -EACCES;
553
554 if (cpu_is_k2e() || cpu_is_k2l())
555 pll_pa_clk_sel();
556
Mugunthan V Nb499a3c2016-08-02 12:01:11 +0530557 priv->net_rx_buffs.buff_ptr = rx_buffs;
558 priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
559 priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
Mugunthan V Nc8386732016-02-02 15:51:33 +0530560
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530561 if (priv->slave_port == 1) {
Grygorii Strashkoa2c2e4a2018-10-31 16:21:45 -0500562#ifndef CONFIG_SOC_K2G
563 keystone2_net_serdes_setup();
564#endif
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530565 /*
566 * Register MDIO bus for slave 0 only, other slave have
567 * to re-use the same
568 */
Grygorii Strashkoa2c2e4a2018-10-31 16:21:45 -0500569 mdio_bus = cpsw_mdio_init("ethernet-mdio",
Marek Behún6f897ec2022-04-11 21:20:55 +0200570 priv->mdio_base,
Grygorii Strashkoa2c2e4a2018-10-31 16:21:45 -0500571 EMAC_MDIO_CLOCK_FREQ,
Ravi Gunasekaran40cea492022-09-22 15:21:23 +0530572 EMAC_MDIO_BUS_FREQ,
573 false);
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530574 if (!mdio_bus) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900575 pr_err("MDIO alloc failed\n");
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530576 return -ENOMEM;
577 }
578 priv->mdio_bus = mdio_bus;
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530579 } else {
580 /* Get the MDIO bus from slave 0 device */
581 struct ks2_eth_priv *parent_priv;
Mugunthan V Nc8386732016-02-02 15:51:33 +0530582
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530583 parent_priv = dev_get_priv(dev->parent);
584 priv->mdio_bus = parent_priv->mdio_bus;
Grygorii Strashkoa2c2e4a2018-10-31 16:21:45 -0500585 priv->mdio_base = parent_priv->mdio_base;
Mugunthan V Nc8386732016-02-02 15:51:33 +0530586 }
587
Mugunthan V Nc8386732016-02-02 15:51:33 +0530588 priv->netcp_pktdma = &netcp_pktdma;
589
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530590 if (priv->has_mdio) {
591 priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
592 dev, priv->phy_if);
Tom Rinica15d0d2022-11-27 10:25:27 -0500593 if (ofnode_valid(priv->phy_ofnode))
594 priv->phydev->node = priv->phy_ofnode;
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530595 phy_config(priv->phydev);
596 }
Mugunthan V Nc8386732016-02-02 15:51:33 +0530597
598 return 0;
599}
600
601int ks2_eth_remove(struct udevice *dev)
602{
603 struct ks2_eth_priv *priv = dev_get_priv(dev);
604
Grygorii Strashkoa2c2e4a2018-10-31 16:21:45 -0500605 cpsw_mdio_free(priv->mdio_bus);
Mugunthan V Nc8386732016-02-02 15:51:33 +0530606
607 return 0;
608}
609
610static const struct eth_ops ks2_eth_ops = {
611 .start = ks2_eth_start,
612 .send = ks2_eth_send,
613 .recv = ks2_eth_recv,
614 .free_pkt = ks2_eth_free_pkt,
615 .stop = ks2_eth_stop,
616 .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
617 .write_hwaddr = ks2_eth_write_hwaddr,
618};
619
Marek Behún1d371f32022-04-11 21:20:54 +0200620static int ks2_bind_one_slave(struct udevice *dev, ofnode slave, ofnode *gbe_0)
Mugunthan V Nc8386732016-02-02 15:51:33 +0530621{
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530622 char *slave_name;
Marek Behún1d371f32022-04-11 21:20:54 +0200623 u32 slave_no;
Marek Behún92336d32022-04-11 21:20:53 +0200624 int ret;
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530625
Marek Behún1d371f32022-04-11 21:20:54 +0200626 if (ofnode_read_u32(slave, "slave-port", &slave_no))
Marek Behún92336d32022-04-11 21:20:53 +0200627 return 0;
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530628
Marek Behún92336d32022-04-11 21:20:53 +0200629 if (gbe_0 && slave_no == 0) {
630 /* This is the current eth device */
631 *gbe_0 = slave;
632 return 0;
633 }
634
635 /* Slave devices to be registered */
636 slave_name = malloc(20);
637 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
Marek Behún1d371f32022-04-11 21:20:54 +0200638 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name, slave,
639 NULL);
Marek Behún92336d32022-04-11 21:20:53 +0200640 if (ret)
641 pr_err("ks2_net - not able to bind slave interfaces\n");
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530642
Marek Behún92336d32022-04-11 21:20:53 +0200643 return ret;
644}
645
Marek Behún1d371f32022-04-11 21:20:54 +0200646static int ks2_eth_bind_slaves(struct udevice *dev, ofnode gbe, ofnode *gbe_0)
Marek Behún92336d32022-04-11 21:20:53 +0200647{
Marek Behún1d371f32022-04-11 21:20:54 +0200648 ofnode interfaces, sec_slave, slave;
649 int ret;
Marek Behún92336d32022-04-11 21:20:53 +0200650
Marek Behún1d371f32022-04-11 21:20:54 +0200651 interfaces = ofnode_find_subnode(gbe, "interfaces");
652 ofnode_for_each_subnode(slave, interfaces) {
Marek Behún92336d32022-04-11 21:20:53 +0200653 ret = ks2_bind_one_slave(dev, slave, gbe_0);
654 if (ret)
655 return ret;
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530656 }
657
Marek Behún1d371f32022-04-11 21:20:54 +0200658 sec_slave = ofnode_find_subnode(gbe, "secondary-slave-ports");
659 ofnode_for_each_subnode(slave, sec_slave) {
Marek Behún92336d32022-04-11 21:20:53 +0200660 ret = ks2_bind_one_slave(dev, slave, NULL);
661 if (ret)
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530662 return ret;
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530663 }
664
665 return 0;
666}
667
Marek Behún1d371f32022-04-11 21:20:54 +0200668static int ks2_eth_parse_slave_interface(ofnode netcp, ofnode slave,
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530669 struct ks2_eth_priv *priv,
670 struct eth_pdata *pdata)
671{
Marek Behún1d371f32022-04-11 21:20:54 +0200672 struct ofnode_phandle_args dma_args;
673 ofnode phy, mdio;
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530674 int dma_count;
Mugunthan V Nc8386732016-02-02 15:51:33 +0530675
Marek Behún1d371f32022-04-11 21:20:54 +0200676 priv->slave_port = ofnode_read_s32_default(slave, "slave-port", -1);
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530677 priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
Mugunthan V Nc8386732016-02-02 15:51:33 +0530678
Mugunthan V Nc8386732016-02-02 15:51:33 +0530679 /* U-Boot slave port number starts with 1 instead of 0 */
680 priv->slave_port += 1;
681
Marek Behún1d371f32022-04-11 21:20:54 +0200682 dma_count = ofnode_count_phandle_with_args(netcp, "ti,navigator-dmas",
683 NULL, 1);
684 if (priv->slave_port < dma_count &&
685 !ofnode_parse_phandle_with_args(netcp, "ti,navigator-dmas", NULL, 1,
686 priv->slave_port - 1, &dma_args))
687 priv->net_rx_buffs.rx_flow = dma_args.args[0];
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530688
Marek Behún1d371f32022-04-11 21:20:54 +0200689 priv->link_type = ofnode_read_s32_default(slave, "link-interface", -1);
Murali Karicheri3c796482019-02-21 12:02:03 -0500690
Marek Behún1d371f32022-04-11 21:20:54 +0200691 phy = ofnode_get_phy_node(slave);
692 priv->phy_ofnode = phy;
693 if (ofnode_valid(phy)) {
694 priv->phy_addr = ofnode_read_s32_default(phy, "reg", -1);
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530695
Marek Behún1d371f32022-04-11 21:20:54 +0200696 mdio = ofnode_get_parent(phy);
697 if (!ofnode_valid(mdio)) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900698 pr_err("mdio dt not found\n");
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530699 return -ENODEV;
700 }
Marek Behún6f897ec2022-04-11 21:20:55 +0200701 priv->mdio_base = ofnode_get_addr(mdio);
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530702 }
Mugunthan V Nc8386732016-02-02 15:51:33 +0530703
Mugunthan V N17819112016-08-11 20:04:03 +0530704 if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
Mugunthan V Nc8386732016-02-02 15:51:33 +0530705 priv->phy_if = PHY_INTERFACE_MODE_SGMII;
706 pdata->phy_interface = priv->phy_if;
707 priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
708 priv->has_mdio = true;
Mugunthan V N17819112016-08-11 20:04:03 +0530709 } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
Marek Behún1d371f32022-04-11 21:20:54 +0200710 priv->phy_if = ofnode_read_phy_mode(slave);
Marek Behún48631e42022-04-07 00:33:03 +0200711 if (priv->phy_if == PHY_INTERFACE_MODE_NA)
Murali Karicheri3c796482019-02-21 12:02:03 -0500712 priv->phy_if = PHY_INTERFACE_MODE_RGMII;
Mugunthan V N17819112016-08-11 20:04:03 +0530713 pdata->phy_interface = priv->phy_if;
Marek Behúnbc194772022-04-07 00:33:01 +0200714
715 if (priv->phy_if != PHY_INTERFACE_MODE_RGMII &&
716 priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID &&
717 priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID &&
718 priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) {
719 pr_err("invalid phy-mode\n");
720 return -EINVAL;
721 }
722
Mugunthan V N17819112016-08-11 20:04:03 +0530723 priv->has_mdio = true;
Mugunthan V Nc8386732016-02-02 15:51:33 +0530724 }
Mugunthan V Nc8386732016-02-02 15:51:33 +0530725
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530726 return 0;
727}
728
Simon Glassaad29ae2020-12-03 16:55:21 -0700729static int ks2_sl_eth_of_to_plat(struct udevice *dev)
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530730{
Marek Behún1d371f32022-04-11 21:20:54 +0200731 ofnode slave, interfaces, gbe, netcp_devices, netcp;
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530732 struct ks2_eth_priv *priv = dev_get_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700733 struct eth_pdata *pdata = dev_get_plat(dev);
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530734
Marek Behún1d371f32022-04-11 21:20:54 +0200735 slave = dev_ofnode(dev);
736 interfaces = ofnode_get_parent(slave);
737 gbe = ofnode_get_parent(interfaces);
738 netcp_devices = ofnode_get_parent(gbe);
739 netcp = ofnode_get_parent(netcp_devices);
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530740
741 ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
742
Marek Behún1d371f32022-04-11 21:20:54 +0200743 pdata->iobase = ofnode_get_addr(netcp);
Mugunthan V Nc8386732016-02-02 15:51:33 +0530744
745 return 0;
746}
747
Simon Glassaad29ae2020-12-03 16:55:21 -0700748static int ks2_eth_of_to_plat(struct udevice *dev)
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530749{
750 struct ks2_eth_priv *priv = dev_get_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700751 struct eth_pdata *pdata = dev_get_plat(dev);
Marek Behún1d371f32022-04-11 21:20:54 +0200752 ofnode netcp_devices, gbe, gbe_0;
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530753
Marek Behún1d371f32022-04-11 21:20:54 +0200754 netcp_devices = dev_read_subnode(dev, "netcp-devices");
755 gbe = ofnode_find_subnode(netcp_devices, "gbe");
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530756
Marek Behún1d371f32022-04-11 21:20:54 +0200757 gbe_0 = ofnode_null();
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530758 ks2_eth_bind_slaves(dev, gbe, &gbe_0);
759
Marek Behún1d371f32022-04-11 21:20:54 +0200760 ks2_eth_parse_slave_interface(dev_ofnode(dev), gbe_0, priv, pdata);
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530761
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900762 pdata->iobase = dev_read_addr(dev);
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530763
764 return 0;
765}
766
Mugunthan V Nc8386732016-02-02 15:51:33 +0530767static const struct udevice_id ks2_eth_ids[] = {
768 { .compatible = "ti,netcp-1.0" },
769 { }
770};
771
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530772U_BOOT_DRIVER(eth_ks2_slave) = {
773 .name = "eth_ks2_sl",
774 .id = UCLASS_ETH,
Simon Glassaad29ae2020-12-03 16:55:21 -0700775 .of_to_plat = ks2_sl_eth_of_to_plat,
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530776 .probe = ks2_eth_probe,
777 .remove = ks2_eth_remove,
778 .ops = &ks2_eth_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700779 .priv_auto = sizeof(struct ks2_eth_priv),
Simon Glass71fa5b42020-12-03 16:55:18 -0700780 .plat_auto = sizeof(struct eth_pdata),
Mugunthan V N1bf9c6f2016-08-02 12:01:12 +0530781 .flags = DM_FLAG_ALLOC_PRIV_DMA,
782};
Mugunthan V Nc8386732016-02-02 15:51:33 +0530783
784U_BOOT_DRIVER(eth_ks2) = {
785 .name = "eth_ks2",
786 .id = UCLASS_ETH,
787 .of_match = ks2_eth_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700788 .of_to_plat = ks2_eth_of_to_plat,
Mugunthan V Nc8386732016-02-02 15:51:33 +0530789 .probe = ks2_eth_probe,
790 .remove = ks2_eth_remove,
791 .ops = &ks2_eth_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700792 .priv_auto = sizeof(struct ks2_eth_priv),
Simon Glass71fa5b42020-12-03 16:55:18 -0700793 .plat_auto = sizeof(struct eth_pdata),
Mugunthan V Nc8386732016-02-02 15:51:33 +0530794 .flags = DM_FLAG_ALLOC_PRIV_DMA,
795};