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git01.mediatek.com / filogic / uboot / 1d52512b2e81dbfae2cf11f6ef886bc22a7cd4d8 / . / drivers / net / ti / davinci_emac.h
blob: c213e24b8b2bdca2ea9d5ee16d9addce00e4edb6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]2/*
3 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
4 *
5 * Based on: mach-davinci/emac_defs.h
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]7 */
8
9#ifndef _DAVINCI_EMAC_H_
10#define _DAVINCI_EMAC_H_
11/* Ethernet Min/Max packet size */
12#define EMAC_MIN_ETHERNET_PKT_SIZE 60
13#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
Ilya Yanokff672762011-11-28 06:37:33 +0000[diff] [blame]14/* Buffer size (should be aligned on 32 byte and cache line) */
15#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
16 ARCH_DMA_MINALIGN)
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]17
18/* Number of RX packet buffers
19 * NOTE: Only 1 buffer supported as of now
20 */
21#define EMAC_MAX_RX_BUFFERS 10
22
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]23/***********************************************
24 ******** Internally used macros ***************
25 ***********************************************/
26
27#define EMAC_CH_TX 1
28#define EMAC_CH_RX 0
29
30/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
31 * reserve space for 64 descriptors max
32 */
33#define EMAC_RX_DESC_BASE 0x0
34#define EMAC_TX_DESC_BASE 0x1000
35
36/* EMAC Teardown value */
37#define EMAC_TEARDOWN_VALUE 0xfffffffc
38
39/* MII Status Register */
40#define MII_STATUS_REG 1
Tom Rinic3cf8992017-05-10 12:01:02 -0400[diff] [blame]41/* PHY Configuration register */
42#define PHY_CONF_TXCLKEN (1 << 5)
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]43
44/* Number of statistics registers */
45#define EMAC_NUM_STATS 36
46
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]47/* EMAC Descriptor */
48typedef volatile struct _emac_desc
49{
50 u_int32_t next; /* Pointer to next descriptor
51 in chain */
52 u_int8_t *buffer; /* Pointer to data buffer */
53 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
54 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
55} emac_desc;
56
57/* CPPI bit positions */
58#define EMAC_CPPI_SOP_BIT (0x80000000)
59#define EMAC_CPPI_EOP_BIT (0x40000000)
60#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
61#define EMAC_CPPI_EOQ_BIT (0x10000000)
62#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
63#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
64
65#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
66
67#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
68#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
69#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
70#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
71#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
72
73#define EMAC_MAC_ADDR_MATCH (1 << 19)
74#define EMAC_MAC_ADDR_IS_VALID (1 << 20)
75
76#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
77#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
78
Ilya Yanok5f732f72011-11-28 06:37:29 +0000[diff] [blame]79#define MDIO_CONTROL_IDLE (0x80000000)
80#define MDIO_CONTROL_ENABLE (0x40000000)
81#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
82#define MDIO_CONTROL_FAULT (0x80000)
83#define MDIO_USERACCESS0_GO (0x80000000)
84#define MDIO_USERACCESS0_WRITE_READ (0x0)
85#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
86#define MDIO_USERACCESS0_ACK (0x20000000)
87
88/* Ethernet MAC Registers Structure */
89typedef struct {
90 dv_reg TXIDVER;
91 dv_reg TXCONTROL;
92 dv_reg TXTEARDOWN;
93 u_int8_t RSVD0[4];
94 dv_reg RXIDVER;
95 dv_reg RXCONTROL;
96 dv_reg RXTEARDOWN;
97 u_int8_t RSVD1[100];
98 dv_reg TXINTSTATRAW;
99 dv_reg TXINTSTATMASKED;
100 dv_reg TXINTMASKSET;
101 dv_reg TXINTMASKCLEAR;
102 dv_reg MACINVECTOR;
103 u_int8_t RSVD2[12];
104 dv_reg RXINTSTATRAW;
105 dv_reg RXINTSTATMASKED;
106 dv_reg RXINTMASKSET;
107 dv_reg RXINTMASKCLEAR;
108 dv_reg MACINTSTATRAW;
109 dv_reg MACINTSTATMASKED;
110 dv_reg MACINTMASKSET;
111 dv_reg MACINTMASKCLEAR;
112 u_int8_t RSVD3[64];
113 dv_reg RXMBPENABLE;
114 dv_reg RXUNICASTSET;
115 dv_reg RXUNICASTCLEAR;
116 dv_reg RXMAXLEN;
117 dv_reg RXBUFFEROFFSET;
118 dv_reg RXFILTERLOWTHRESH;
119 u_int8_t RSVD4[8];
120 dv_reg RX0FLOWTHRESH;
121 dv_reg RX1FLOWTHRESH;
122 dv_reg RX2FLOWTHRESH;
123 dv_reg RX3FLOWTHRESH;
124 dv_reg RX4FLOWTHRESH;
125 dv_reg RX5FLOWTHRESH;
126 dv_reg RX6FLOWTHRESH;
127 dv_reg RX7FLOWTHRESH;
128 dv_reg RX0FREEBUFFER;
129 dv_reg RX1FREEBUFFER;
130 dv_reg RX2FREEBUFFER;
131 dv_reg RX3FREEBUFFER;
132 dv_reg RX4FREEBUFFER;
133 dv_reg RX5FREEBUFFER;
134 dv_reg RX6FREEBUFFER;
135 dv_reg RX7FREEBUFFER;
136 dv_reg MACCONTROL;
137 dv_reg MACSTATUS;
138 dv_reg EMCONTROL;
139 dv_reg FIFOCONTROL;
140 dv_reg MACCONFIG;
141 dv_reg SOFTRESET;
142 u_int8_t RSVD5[88];
143 dv_reg MACSRCADDRLO;
144 dv_reg MACSRCADDRHI;
145 dv_reg MACHASH1;
146 dv_reg MACHASH2;
147 dv_reg BOFFTEST;
148 dv_reg TPACETEST;
149 dv_reg RXPAUSE;
150 dv_reg TXPAUSE;
151 u_int8_t RSVD6[16];
152 dv_reg RXGOODFRAMES;
153 dv_reg RXBCASTFRAMES;
154 dv_reg RXMCASTFRAMES;
155 dv_reg RXPAUSEFRAMES;
156 dv_reg RXCRCERRORS;
157 dv_reg RXALIGNCODEERRORS;
158 dv_reg RXOVERSIZED;
159 dv_reg RXJABBER;
160 dv_reg RXUNDERSIZED;
161 dv_reg RXFRAGMENTS;
162 dv_reg RXFILTERED;
163 dv_reg RXQOSFILTERED;
164 dv_reg RXOCTETS;
165 dv_reg TXGOODFRAMES;
166 dv_reg TXBCASTFRAMES;
167 dv_reg TXMCASTFRAMES;
168 dv_reg TXPAUSEFRAMES;
169 dv_reg TXDEFERRED;
170 dv_reg TXCOLLISION;
171 dv_reg TXSINGLECOLL;
172 dv_reg TXMULTICOLL;
173 dv_reg TXEXCESSIVECOLL;
174 dv_reg TXLATECOLL;
175 dv_reg TXUNDERRUN;
176 dv_reg TXCARRIERSENSE;
177 dv_reg TXOCTETS;
178 dv_reg FRAME64;
179 dv_reg FRAME65T127;
180 dv_reg FRAME128T255;
181 dv_reg FRAME256T511;
182 dv_reg FRAME512T1023;
183 dv_reg FRAME1024TUP;
184 dv_reg NETOCTETS;
185 dv_reg RXSOFOVERRUNS;
186 dv_reg RXMOFOVERRUNS;
187 dv_reg RXDMAOVERRUNS;
188 u_int8_t RSVD7[624];
189 dv_reg MACADDRLO;
190 dv_reg MACADDRHI;
191 dv_reg MACINDEX;
192 u_int8_t RSVD8[244];
193 dv_reg TX0HDP;
194 dv_reg TX1HDP;
195 dv_reg TX2HDP;
196 dv_reg TX3HDP;
197 dv_reg TX4HDP;
198 dv_reg TX5HDP;
199 dv_reg TX6HDP;
200 dv_reg TX7HDP;
201 dv_reg RX0HDP;
202 dv_reg RX1HDP;
203 dv_reg RX2HDP;
204 dv_reg RX3HDP;
205 dv_reg RX4HDP;
206 dv_reg RX5HDP;
207 dv_reg RX6HDP;
208 dv_reg RX7HDP;
209 dv_reg TX0CP;
210 dv_reg TX1CP;
211 dv_reg TX2CP;
212 dv_reg TX3CP;
213 dv_reg TX4CP;
214 dv_reg TX5CP;
215 dv_reg TX6CP;
216 dv_reg TX7CP;
217 dv_reg RX0CP;
218 dv_reg RX1CP;
219 dv_reg RX2CP;
220 dv_reg RX3CP;
221 dv_reg RX4CP;
222 dv_reg RX5CP;
223 dv_reg RX6CP;
224 dv_reg RX7CP;
225} emac_regs;
226
227/* EMAC Wrapper Registers Structure */
228typedef struct {
229#ifdef DAVINCI_EMAC_VERSION2
230 dv_reg idver;
231 dv_reg softrst;
232 dv_reg emctrl;
233 dv_reg c0rxthreshen;
234 dv_reg c0rxen;
235 dv_reg c0txen;
236 dv_reg c0miscen;
237 dv_reg c1rxthreshen;
238 dv_reg c1rxen;
239 dv_reg c1txen;
240 dv_reg c1miscen;
241 dv_reg c2rxthreshen;
242 dv_reg c2rxen;
243 dv_reg c2txen;
244 dv_reg c2miscen;
245 dv_reg c0rxthreshstat;
246 dv_reg c0rxstat;
247 dv_reg c0txstat;
248 dv_reg c0miscstat;
249 dv_reg c1rxthreshstat;
250 dv_reg c1rxstat;
251 dv_reg c1txstat;
252 dv_reg c1miscstat;
253 dv_reg c2rxthreshstat;
254 dv_reg c2rxstat;
255 dv_reg c2txstat;
256 dv_reg c2miscstat;
257 dv_reg c0rximax;
258 dv_reg c0tximax;
259 dv_reg c1rximax;
260 dv_reg c1tximax;
261 dv_reg c2rximax;
262 dv_reg c2tximax;
263#else
264 u_int8_t RSVD0[4100];
265 dv_reg EWCTL;
266 dv_reg EWINTTCNT;
267#endif
268} ewrap_regs;
269
270/* EMAC MDIO Registers Structure */
271typedef struct {
272 dv_reg VERSION;
273 dv_reg CONTROL;
274 dv_reg ALIVE;
275 dv_reg LINK;
276 dv_reg LINKINTRAW;
277 dv_reg LINKINTMASKED;
278 u_int8_t RSVD0[8];
279 dv_reg USERINTRAW;
280 dv_reg USERINTMASKED;
281 dv_reg USERINTMASKSET;
282 dv_reg USERINTMASKCLEAR;
283 u_int8_t RSVD1[80];
284 dv_reg USERACCESS0;
285 dv_reg USERPHYSEL0;
286 dv_reg USERACCESS1;
287 dv_reg USERPHYSEL1;
288} mdio_regs;
289
290int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
291int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
292
293typedef struct {
294 char name[64];
295 int (*init)(int phy_addr);
296 int (*is_phy_connected)(int phy_addr);
297 int (*get_link_speed)(int phy_addr);
298 int (*auto_negotiate)(int phy_addr);
299} phy_t;
300
301#endif /* _DAVINCI_EMAC_H_ */