| Simon Glass | 131a645 | 2015-04-28 20:25:09 -0600 | [diff] [blame] | 1 | config CPU |
| 2 | bool "Enable CPU drivers using Driver Model" |
| 3 | help |
| 4 | This allows drivers to be provided for CPUs and their type to be |
| 5 | specified in the board's device tree. For boards which support |
| 6 | multiple CPUs, then normally have to be set up in U-Boot so that |
| 7 | they can work correctly in the OS. This provides a framework for |
| 8 | finding out information about available CPUs and making changes. |
| Mario Six | 28fbefa | 2018-08-06 10:23:45 +0200 | [diff] [blame] | 9 | |
| Peng Fan | 146cce9 | 2023-04-28 12:08:12 +0800 | [diff] [blame] | 10 | config CPU_IMX |
| 11 | bool "Enable i.MX CPU driver" |
| 12 | depends on CPU && ARM64 |
| 13 | help |
| 14 | Support CPU cores for SoCs of the i.MX series. |
| 15 | |
| Mario Six | 28fbefa | 2018-08-06 10:23:45 +0200 | [diff] [blame] | 16 | config CPU_MPC83XX |
| 17 | bool "Enable MPC83xx CPU driver" |
| Michal Simek | b1f26e9 | 2022-04-22 15:32:21 +0200 | [diff] [blame] | 18 | depends on CPU && MPC83xx |
| Mario Six | 28fbefa | 2018-08-06 10:23:45 +0200 | [diff] [blame] | 19 | select CLK_MPC83XX |
| 20 | help |
| 21 | Support CPU cores for SoCs of the MPC83xx series. |
| Bin Meng | c4fcb62 | 2018-12-12 06:12:26 -0800 | [diff] [blame] | 22 | |
| 23 | config CPU_RISCV |
| 24 | bool "Enable RISC-V CPU driver" |
| 25 | depends on CPU && RISCV |
| 26 | help |
| 27 | Support CPU cores for RISC-V architecture. |
| Ovidiu Panait | 64be978 | 2022-05-31 21:14:35 +0300 | [diff] [blame] | 28 | |
| 29 | config CPU_MICROBLAZE |
| 30 | bool "Enable Microblaze CPU driver" |
| 31 | depends on CPU && MICROBLAZE |
| Ovidiu Panait | 64be978 | 2022-05-31 21:14:35 +0300 | [diff] [blame] | 32 | select DM_EVENT |
| 33 | select XILINX_MICROBLAZE0_PVR |
| 34 | help |
| 35 | Support CPU cores for Microblaze architecture. |
| Jiaxun Yang | 8b31abf | 2024-06-18 14:56:07 +0100 | [diff] [blame] | 36 | |
| 37 | config CPU_XTENSA |
| 38 | bool "Enable Xtensa CPU driver" |
| 39 | depends on CPU && XTENSA |
| 40 | help |
| 41 | Support CPU cores for Xtensa architecture. |