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git01.mediatek.com / filogic / uboot / 1d52512b2e81dbfae2cf11f6ef886bc22a7cd4d8 / . / doc / usage / cmd / mtrr.rst
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Simon Glass23ec2942023-07-15 21:38:37 -0600[diff] [blame]1.. SPDX-License-Identifier: GPL-2.0+:
2
Heinrich Schuchardt1b0c3162024-01-14 14:53:13 +0100[diff] [blame]3.. index::
4 single: mtrr (command)
5
Simon Glass23ec2942023-07-15 21:38:37 -0600[diff] [blame]6mtrr command
7============
8
Heinrich Schuchardt44b09b32024-03-16 11:09:36 +0100[diff] [blame]9Synopsis
10--------
Simon Glass23ec2942023-07-15 21:38:37 -0600[diff] [blame]11
12 mtrr [list]
13 mtrr set <reg> <type> <start> <size>
14 mtrr disable <reg>
15 mtrr enable
16
17
18Description
19-----------
20
21The *mtrr* command is used to dump the Memory Type Range Registers (MTRRs) on
22an x86 machine. These register control cache behaviour in selected memory
23ranges.
24
25Note that the number of registers can vary between CPUs.
26
27
28mtrr [list]
29~~~~~~~~~~~
30
31List the MTRRs. The table shows the following information:
32
33Reg
34 Register number (the first is register 0)
35
36Valid
37 Shows Y if the register is valid (has bit 11 set), N if not
38
39Write-type
40 Shows the behaviour when writing to the memory region. The types are
41 abbreviated to fit a reasonable line length. Valid types shown below.
42
43 ====== ============== ====================================================
44 Value Type Meaning
45 ====== ============== ====================================================
46 0 Uncacheable Skip cache and write directly to memory
47 1 Combine Multiple writes can be combined into one transaction
48 4 Through Update cache and also write to memory
49 5 Protect Writes are prohibited
50 6 Back Update cache but don't write to memory
51 ====== ============== ====================================================
52
53Base
54 Base memory address from which the register controls behaviour
55
56Mask
57 Mask value, which also indicates the size
58
59Size
60 Length of memory region within which the register controls behaviour
61
62
63mtrr set
64~~~~~~~~
65
66This sets the value of a particular MTRR. Parameters are:
67
68reg
69 Register number to set, with 0 being the first
70
71type
72 Access type to set. See Write-type above for valid types. This uses the name
73 rather than its numeric value.
74
75start
76 Base memory address from which the register should control behaviour
77
78size
79 Length of memory region within which the register controls behaviour
80
81
82mtrr disable
83~~~~~~~~~~~~
84
85This disables a particular register, by clearing its `valid` bit (11).
86
87
88mtrr enable
89~~~~~~~~~~~
90
91This enables a particular register, by setting its `valid` bit (11).
92
93
94Example
95-------
96
97This shows disabling and enabling an MTRR, as well as setting its type::
98
99 => mtrr
100 CPU 0:
101 Reg Valid Write-type Base || Mask || Size ||
102 0 Y Back 0000000000000000 0000000f80000000 0000000080000000
103 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
104 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
105 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
106 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
107 5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000
108 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
109 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
110 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
111 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
112 => mtrr d 5
113 => mtrr
114 CPU 0:
115 Reg Valid Write-type Base || Mask || Size ||
116 0 Y Back 0000000000000000 0000000f80000000 0000000080000000
117 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
118 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
119 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
120 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
121 5 N Combine 00000000d0000000 0000000ff0000000 0000000010000000
122 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
123 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
124 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
125 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
126 => mtrr e 5
127 => mtrr
128 CPU 0:
129 Reg Valid Write-type Base || Mask || Size ||
130 0 Y Back 0000000000000000 0000000f80000000 0000000080000000
131 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
132 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
133 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
134 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
135 5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000
136 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
137 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
138 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
139 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
140 => mtrr set 5 Uncacheable d0000000 10000000
141 => mtrr
142 CPU 0:
143 Reg Valid Write-type Base || Mask || Size ||
144 0 Y Back 0000000000000000 0000000f80000000 0000000080000000
145 1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
146 2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
147 3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
148 4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
149 5 Y Uncacheable 00000000d0000000 0000000ff0000000 0000000010000000
150 6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
151 7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
152 8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
153 9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
154 =>